VGA timing Driver Module

'Timescale 1ns/1 PS

Module vga_driver # (parameter image_x = 1056,

Image_y= 628,

H_front = 40,

H_back = 88,

Hsync_l = 128,

V_front = 1,

V_back = 23,

Vsync_l = 4,

Datawidth = 8,

Output_reg = 0

)

(

Input CLK,

Input rst_n,

Input [DATAWIDTH-1: 0] Rin,

Input [DATAWIDTH-1: 0] gin,

Input [DATAWIDTH-1: 0] bin,

Output Reg data_req,

Output Reg vsync,

Output Reg hsync,

Output Reg de,

Output Reg [DATAWIDTH-1: 0] rout,

Output Reg [DATAWIDTH-1: 0] gout,

Output Reg [DATAWIDTH-1: 0] bout

);

 

Reg [12: 0] hcnt; Reg [12: 0] vcnt;

[Email protected] (posedge CLK or negedge rst_n)

Begin

If (~ Rst_n)

Hcnt <= 13 'd0;

Else if (hcnt = IMAGE_X-1)

Hcnt <= 13 'd0;

Else

Hcnt <= hcnt + 13 'd1;

End

[Email protected] (posedge CLK or negedge rst_n)

Begin

If (~ Rst_n)

Vcnt <= 12'd0;

Else if (hcnt = IMAGE_X-1)

Begin

If (vcnt = IMAGE_Y-1)

Vcnt <= 12'd0;

Else

Vcnt <= vcnt + 12'd1;

End

End

[Email protected] (posedge CLK or negedge rst_n)

Begin

If (~ Rst_n)

Hsync <= 1' B0;

Else if (hcnt> = H_FRONT-1) & (hcnt

Hsync <= 1' B1;

Else

Hsync <= 1' B0;

End

[Email protected] (posedge CLK or negedge rst_n)

Begin

If (~ Rst_n)

Vsync <= 1' B0;

Else if (hcnt = IMAGE_X-1)

Begin

If (vcnt >=V_FRONT-1) & (vcnt <v_front + VSYNC_L-1 ))

Vsync <= 1' B1;

Else vsync <= 1' B0;

End

End

[Email protected] (posedge CLK or negedge rst_n)

Begin

If (~ Rst_n)

De <= 1 'b0;

Else if (vcnt <v_front + vsync_l + v_back)

De <= 1 'b0;

Else if (hcnt> = h_front + hsync_l + H_BACK-1) & (hcnt <IMAGE_X-1 ))

De <= 1 'b1;

Else

De <= 1 'b0;

End

[Email protected] (posedge CLK or negedge rst_n)

Begin

If (~ Rst_n)

Data_req <= 1 'b0;

Else if (vcnt <v_front + vsync_l + v_back)

Data_req <= 1 'b0;

Else if (hcnt> = h_front + hsync_l + H_BACK-OUTPUT_REG-2) & (hcnt <IMAGE_X-2-OUTPUT_REG ))

Data_req <= 1 'b1;

Else data_req <= 1 'b0;

End

[Email protected] (posedge CLK or negedge rst_n)

Begin

If (~ Rst_n)

Rout <= 10'd0;

Else

Rout <= Rin;

End

[Email protected] (posedge CLK or negedge rst_n)

Begin

If (~ Rst_n)

Gout <= 10'd0;

Else

Gout <= gin;

End

[Email protected] (posedge CLK or negedge rst_n)

Begin

If (~ Rst_n)

Bout <= 10'd0;

Else

Bout <= bin;

End

 

Endmodule

VGA timing Driver Module