Xilinx zynq702c Dual-core non-operating system communication configuration

Recent research in Xilinx ZYNQ7000 found that the xapp1079-amp-bare-metal-cortex-a9.pdf was unable to achieve dual-core communication in VIVADO14.1SDK, after several days of research to achieve communication              General steps in accordance with official documentation, the following are different: 1: When you build FSBL with the new version of Vivado14.1, you add librsa.a if you do not add a compile report-lrsa error 2: Add app_cpu0 and APP_CPU1, use the new version of the Lscript.ld file (need to modify the configuration address shown below), if you do not use the compiler fiq_stack, undef_stack error