Zedboard (ii) Development of embedded applications using VIVADO+SDK-instance One

The introduction of the hardware Platform +SDK Development application (Zedboard Bare Metal development) of the Zedboard Development Board built with Vivado

The process is as follows:

First, the operation of Vivado, the establishment of new projects

Specify a good project path, next, select RTL Project, tick "do not specify sources for this time" (no source files and pin constraints are added first)

　　

Next select the corresponding Development Board, tick board, select Zedboard XXXX

　　　

The final interface shows the information about the new project:

　　

Click Finish to complete.

Second, add the processor zynq-7000 (IP) Core

　　Click on the left menu bar flow navigator->ip intergrstor->create Block Design

　　

Fill in the name, choose the folder (in fact, the sources)

　　

Click the Add IP plus sign in the development interface to search for the IP cores you want to add by entering keywords

　　

When the IP core is selected, the system will display the IP core as a graphical interface:

　　

Click Run Block Automation in the light green stripe

　　

Tick apply board preset to map this IP-core-related input/output signal to the chip-specific pin and add the necessary constraints.

Click the OK button to start the automation, after completing the results such as:

　　

You can change its internal configuration by double-clicking the IP Core in the diagram (the pattern turns orange).

The M_AXI_GP0 is enabled by default and can be controlled by connecting the PL section with AXI from the IP of the interface to PS. Here we temporarily do not have to the PL section, so disable it, otherwise the validation design will be error. Double-click the block to see

　　

When the configuration is complete, right-click on the pattern and select "Validate design" for rule checking.

　　

If there are no errors, the following prompt appears:

　　

　　The next step is to generate the output file and encapsulate it in HDL form

To generate the relevant synthesis, implementation, and simulation files for the modules added above, click Flow navigator->ip intergrstor->generator block Design

　　

　　

After the output file is generated, it is encapsulated as a top-level HDL file, the source window right-click on the core (added IP core name), select Create HDL Wrapper

　　

When finished, the source window has an extra HDL file core_wrapper.v

　　

At this point, we have completed an internal design of an IP core and encapsulated it into a basic HDL form (which can be called by other designs as a module), then RTL analysis, synthesis, implementation, and generation of hardware bitstream files

　　Next, we will generate a bitstream file:

Left navigation bar Flow Navigator->program and debug->generate bitstream, if not previously synthesized and implemented, the system will prompt whether or not, click Yes.

　　

Third, use the SDK to complete the software development

In the previous step we have completed the design of the processor hardware architecture, if the bitstream file is downloaded to the inside of the ZYNQ-7000 chip, then the chip will be a user's own custom processor, but it also lacks software programs.

In this section, we import the hardware platform information into the SDK

Open the project core and select implementation (this step is required, otherwise an error will be followed)

Then File->exprot->exprot Hardware for SDK, the hardware platform information, hardware bit files are all imported into the SDK platform and open the SDK software (open the SDK SYSTEM.HDF is)

　　

Note Check the Add bitstream file

　　

After the build is complete, we have completed the construction of the hardware platform, the next step is to enter the SDK for application software development.

File->launch SDK,SDK starts running.

The left column can see that the hardware platform information has been imported.

　　

　　The next step is to create a BSP (board-level driver package) and application Project (application)

BSP is an essential component for running programs on a hardware platform, select File->new->board Support packages in the SDK

* Bare Metal Development Select standalone

After clicking Finish, the configuration information for the newly created BSP will appear:

　　

Here we have the default configuration, click OK

The next step is to build an application project and select File->new->Application project in the SDK.

　　

Name and select information, click Next when you are done,

　　

Choose Hello World as the project template, Finish. At this point the project browser on the left has just created the project folder, drop-down menu src found HELLOWORLD.C, double-click to edit the

　　

Edit the code, click Save, and then compile.

　　

View the compilation report in the console and compile successfully if no error occurs. The next step is to connect the Zedboard for board-level debugging.

Four, the board level debugging

　　Once the application has been written and compiled successfully, the next step is to connect the PC and Zedboard for debugging.

First, 2 MICRO-USB connections are required, respectively connecting the J14 (UART) and J17 (JTAG), as shown in.

　　

Here is a little explanation of the effect of the two interfaces of J14 and J17:

(1) J14 is a USB to UART serial port, here is used to output the card information (such as the simplest is the output "Hello world" statement, to connect this line in the SDK console display)

(2) J17 is the Usb-jtag configuration port, used to configure the card information

When the line is connected, the jump cap jp7-11 all ground (into JTAG mode) as shown in:

　　

Switch on the Zedboard power supply, turn on the power switch on, and view the port via the PC's "Device Manager".

　　

Be careful to identify which COM port is UART and use it later.

Back to SDK, right-click on Project Lidar->run as->run configurations

　　

Double-click on Xilinx C + + application (GDB), the "project name Debug" appears, select the Right stdio Connection page

Tick "Connect STDIO xxxx", the port dropdown to select the UART corresponding COM number (for example, my is COM4), the following is the value set to 115200, click Apply and then close

　　

After setting up, we can start the board level debugging, click the menu bar button to enter the run model (of course, the above you apply directly after the run is the same effect)

* If you want to step-by-step debugging, click the button to enter the debug mode.

* You may be prompted not to configure the FPGA, skip just fine.

You can view the output through the console.

At this point, a simple application is complete.

In retrospect, the entire process consists of the following stages:

1. Build the hardware platform (in Vivado)

2. Import hardware platform information (including bitstream files) into the SDK

3. Build the driver package and application engineering in the SDK

4. Connect the PC and Development Board for board-level commissioning

　　

　　

Zedboard (ii) Development of embedded applications using VIVADO+SDK-instance One