Flag Register PSW and assembly conditional transfer instruction interpretation

Flag Register PSW

Flag Register PSW (program status Word register PSW)
The flag register PSW is a 16 register. It reflects the state characteristics of the CPU operation and holds some control flags. 8086 uses 9 bits in 16 bits, including 6 status flag bits and 3 control flag bits.

CF (Carry flag bit): When performing an addition (subtraction) operation, the highest bit yields a carry (or borrow), CF is 1, otherwise 0.
ZF 0 Flag bit: If the current operation result is zero, then ZF is 1, otherwise 0.
SF symbol flag bit: The flag bit is the same as the highest bit of the result of the operation. That is, if the result of the operation is negative, SF is 1, otherwise 0.
of overflow flag bits: If the result of the operation exceeds the range that the machine can represent is called overflow, at this time of 1, otherwise 0. The method of judging whether to overflow is: When binary operation is performed, the carry value of the highest bit is XOR with the carry value of the secondary high, if the result of the operation is 1 it is overflow of=1, otherwise of=0

PF parity flag: When the minimum 16 bits of the result of the operation contain an even number of 1 pf=1 otherwise pf=0
AF auxiliary Carry flag: The result of an addition (subtraction) operation is a low 4-bit high 4-bit with a carry (or borrow) when it is af=1 otherwise af=0

There are also three control flag bits to control the operation of the CPU, which can be set and reset by the program.
TF trace flag: This flag bit is set for aspect program debugging. If the TF=1,8086/8088CPU is in a single-step mode of operation, the interrupt is generated after each instruction execution is completed.
If interrupt flag bit: This flag bit is used to control whether the CPU responds to a masked interrupt. If the if=1 is allowed to interrupt, otherwise the interruption is forbidden.
DF Direction flag: This flag bit is used to control the processing direction of the string processing instructions. If df=1 the address automatically decrements during the string processing, otherwise automatically increments.

OD can see 8 flag bits except if sign

Assembly Conditional Transfer Instruction interpretation

The following procedures can be used to understand the above signed conditional transfer instructions

voidMain () {intA=3, b=5; if(a!=b)//JE        if(a==b)//jnz            if(a<=b)//JG                if(A&LT;B)//Jge                    if(a>=b)//JL                        if(A&GT;B)//Jle{printf ("Do if"); }}return 0;

Flag Register PSW and assembly conditional transfer instruction interpretation