Abstract
In the past, only C ++ or C # coloring methods were available when I switched to the kernel-Based Kernel, I have added the keyword of 2001. Now, the blog posts can also show you how to use the golden color !!
Introduction
The following is a typical example of the Verilog Ry-based code. Currently, keyword can be correctly displayed. This is a great deal of action ....
1 Module Checksum_task_logic (
2 Input CLK,
3 Input Reset_n,
4 Input Go,
5 Input Data_in_ready,
6 Input [ 31 : 0 ] Data_to_process,
7 Output [ 15 : 0 ] Result
8 );
9
10 Reg Data_in_ready_delay;
11 Reg [ 31 : 0 ] Data_in_reg;
12 Reg [ 31 : 0 ] Sum_reg;
13
14 Wire [ 31 : 0 ] Sum_1;
15 Wire [ 31 : 0 ] Sum_2;
16 Wire [ 31 : 0 ] Sum_3;
17 Wire [ 31 : 0 ] Next_sum_reg;
18
19 // First adder stage (16-bits) fold upper and lower half
20 Assign Sum_1 = Data_in_reg [ 31 : 16 ] + Data_in_reg [ 15 : 0 ];
21
22 // Second adder state (32-bits) of sum_1 and previusly stored sum (sum_reg)
23 Assign Next_sum_reg = Sum_1 + Sum_reg;
24
25 // Fold in upper (carry count) and lower half of sum register
26 Assign Sum_2 = Sum_reg [ 31 : 16 ] + Sum_reg [ 15 : 0 ];
27
28 // Fold in upper (possible carry) and lower half of sum_2
29 Assign Sum_3 = Sum_2 [ 31 : 16 ] + Sum_2 [ 15 : 0 ];
30
31 // Invert the sum (one's complement) for result
32 Assign Result = { ~ (Sum_3 [ 15 : 0 ])};
33
34 // Delay register for data_in_ready
35 Always @( Posedge CLK Or Negedge Reset_n) Begin
36 If (Reset_n = 1 ' B0)
37 Data_in_ready_delay <= 1 ' B0;
38 Else
39 Data_in_ready_delay <= Data_in_ready;
40 End // Always @
41
42 // Write to the data_in register
43 Always @( Posedge CLK Or Negedge Reset_n) Begin
44 If (Reset_n = 1 ' B0)
45 Data_in_reg <= 32 ' H00000000;
46 Else
47 Data_in_reg <= Data_to_process;
48 End // Always @
49
50 // Write to the sum register the next value
51 Always @( Posedge CLK Or Negedge Reset_n) Begin
52 If (Reset_n = 1 ' B0)
53 Sum_reg <= 32 ' H00000000;
54 Else If (GO) // Clears sum_reg at start of checksum Calculation
55 Sum_reg <= 32 ' H1__0000;
56 Else If (Data_in_ready_delay = 1 ' B1)
57 Sum_reg <= Next_sum_reg;
58 Else
59 Sum_reg <= Sum_reg;
60 End // Always @
61
62 Endmodule
