Four-network chip Simulation for Skyeye hardware simulation [embedded]

The third part of this series mainly introduces the implementation details of the Skyeye hardware simulation platform. The main content includes the overall design of Skyeye, the Scalable framework of Skyeye, the key data structure of Skyeye, the simulation implementation of Skyeye on various CPUs, the simulation implementation of Skyeye on various peripherals, and how to install and use Skyeye and how to expand the simulation module of Skyeye. An in-depth understanding of Skyeye helps to gain a deeper understanding of embedded hardware systems, especially how the operating system and driver interact with embedded hardware systems.

Skyeye Network Simulation Implementation

1. conception and design overview of RTL8019AS network chip Simulation

Currently, networks are widely used in embedded systems. By adding virtual ethernet chip devices to Skyeye, Skyeye supports Ethernet network interface simulation. In this way, the operating system running on the Skyeye hardware simulation platform can communicate with the local Linux host over the network. Of course, packet forwarding mechanisms such as ipchains/iptables can further support direct communication with the Internet.

In view of the widespread use of ne2k 10base-t compatible network chips in embedded devices, RTL8019AS is a representative and convenient to purchase, we decided to simulate it. The design scheme is completely based on the real RTL8019AS (ne2000 compatible, 8019as), but is simplified in part. The simplified parts mainly include:

• Some status registers. It mainly refers to the status information of sending and receiving data packets, which is rarely used in embedded systems. Therefore, simulation is not added for the time being.
• 16-Bit mode DMA. For ne2k chips, the 8-bit DMA and 16-bit DMA modes only differ in data transmission efficiency, but they are not very important for Skyeye, therefore, only the 8-bit DMA mode is simulated.
  
• The remote DMA read mode in which the CPU receives data packets from the network chip. Because 8019as provides another more efficient send command method to receive data packets, the remote DMA read is not simulated for simplicity.

Currently, virtual ethernet chip devices are designed to simplify the principle of putting the driver of the virtual network chip on a real 8019as network chip, which can be used directly, currently, the ne2k driver on other systems cannot be used directly on Skyeye.

2. Principles of virtual 8019as network chip

Skyeye is a hardware development board simulator. The virtual 8019as network chip is a relatively independent external device on the Virtual Development Board. This device has its own internal data structure and operation functions to complete relevant functions. However, the external interface of the virtual 8019as network chip is only a few API functions provided to Skyeye and the system resources it occupies, such as memory map Io and IRQ. What the network chip driver sees is the 8019as register and the system interrupt number it occupies. These register addresses are located in an IO address space in the Development Board of Skyeye simulation, what Skyeye sees is the register address and the API function provided by the virtual 8019as network chip to Skyeye. If the network chip driver running on the Virtual Development Board reads and writes these register addresses, Skyeye intercepts these read and write operations, and convert them into calls to the functions nic_read and nic_write of the virtual 8019as network chip API, so as to operate the virtual 8019as network chip and send and receive data. This process is consistent with the logic operation of the real hardware system.

So how does Skyeye communicate with the host while switching data packets with the virtual 8019as network chip? This is achieved through the tun/TAP or vnet virtual network interface installed on the Linux host. TUN/TAP and vnet are a kernel module in the Linux kernel. They simulate a simple point-to-point network environment, which will be further described later. The overall structure of the virtual 8019as network chip is as follows:

Figure 0-1 8019as simulation structure

3. Memory Structure of virtual 8019as network chip

The virtual 8019as network chip simulated by Skyeye works in 8-Bit mode. The network chip contains 8 K bytes of Ram and the address is 0x4000-0x5fff (refers to the storage address on the network chip, instead of the isa bus address, it is the memory used by the network chip to work. Every 256 bytes is called a page with a total of 64 pages. The page address is the 8-bit high address, and the page address is 0x00 -- 0xff.

First, let's take a look at page 0x40-0x5f. Part of the 8 k ram is used to store the received data packet, and part of the Ram is used to store the data packet to be sent, which is determined by the driver compiler. (Generally, only one maximum Ethernet package can be accommodated. Therefore, it is defined as page 0x40-0x45, that is, page 0x4000-0x45ff, which is about 1.5 K. The rest are used for collecting packets ). According to the provisions in the 8019as hardware specification manual, only-5fff can be used in 8-bit working mode, and 6000-7fff RAM can be used in 16-Bit mode.

Figure 0-2 Ram Space Structure of ne2k compatible network chip

Let's take a look at page 1, that is, the prom in Figure 0 6, which is read from 93c46 when the network chip is powered on and reset, 0x00-0x0b (working in 8-bit DMA mode) is used to store the MAC address of the current node. The content of the parity address is retained. For example, if the MAC address 00 00 12 34 56 78 is stored in 0x00-0x0b, It is 00 00 00 00 00 12 12 12 34 56 56 78 78. The content of a single address and dual address is repeated, generally, the content of an even address is used to adapt to both 8-bit and 16-bit DMA. A 93c46 EEPROM is added to the 8019 chip. When powered on, the MAC address is automatically read from 93c46 to the prom. Therefore, to write the driver for the virtual network chip, you only need to read the MAC address in the prom in the init function, and write the work register PAR0-PAR5. The IP address of the network chip is determined based on these registers and is independent of the prom and 93c46. Other addresses of the prom cannot be used. It is worth mentioning that, although a MAC address can be obtained at will, the highest byte cannot be an odd number; otherwise, it is a multicast.
MAC address, which may cause problems in future applications.

Based on the above analysis, the virtual 8019as network chip has two internal RAM blocks to simulate:

0x0000-0x000b, 12 bytes, page number 0x00. Store MAC addresses

0x4000-0x5fff, 8192 bytes, page number 0x40-0x60 (only 0x5f is used, and 0x60 is the end boundary), used to store the data packet buffer sent and received. The specific number of sent and received data packets is determined by the driver initialization.

The above two memories are internal data of the network chip and are not in the system address space. In fact, the CPU simulated by Skyeye cannot see these two memories and can only be accessed indirectly through read/write registers.

4. Register structure of virtual 8019as network chip

In RTL8019AS or other ne2k compatible network chips, the software reads and writes the memory of the network chip through a data register (address offset 0x10) in the form of DMA, the DMA length and start address are determined by the Control Register. However, DMA is divided into remote DMA and local DMA. The two types of DMA are explained first:

Local DMA Ethernet network chip RAM

Remote DMA Network chip RAM host

Local DMA is the network chip to automatically send and receive data to/from the network chip RAM, while remote DMA is the CPU to actively read and write data from the network chip RAM to/from the CPU Ram. The specific read/write operations can be divided into three types:

• CPU reads/writes data to a network chip
  The control method is to set the following control registers:
  • Rbcr0, rbcr1: the length of data to be read/written
  • Rsar0, rsar1: the starting address for storing data in the network chip RAM (instead of the page number, but usually starts from 00 of a page, such as 0X4000)
  • Cr: sends the remote DMA start command to the command register

  Then you can read and write data through the data register, with a width of 8 bits.

• Network chips send data to Ethernet
  After the CPU sends data to the network chip using remote DMA, the network chip can send data externally using local DMA.
  You need to set the following control registers:
  • Tpsr: the start page number of the data to be sent by the network chip in the network chip RAM. Therefore, data sent can only be stored at the beginning of a page.
  • Tbcr0, tbcr1: total length of data to be sent
  • Cr: the command to send data packets to the command register pai_xmit.

  Then the program can return the packet, and the network chip will automatically send the packet with local DMA.

• Network Chip reads data from Ethernet
  The registers used by the network chip to read data from the Ethernet are as follows:
  • Pstart and pstop: start and end page numbers of the buffer for receiving data from the network chip. Form a receiving buffer ring. 256 bytes per page
  • Curr: receives the buffer ring write page pointer, initialization = pstart
  • Bnry: receives the buffer ring read page pointer, initialization = pstart

The four registers are initialized in the init function. When data packets arrive, the network chip automatically determines whether to send the packets to the local machine. If yes, the local DMA is used to store the data and the read/write pointer is automatically modified.

Figure 0-3 DMA-related registers

The Register address of 8019as is 0x00-0x1f. There are 4 pages in page 0-3. Each page is accessed with 0x00-0x0f, but actually accessed is a different register. The registers in page 3 are dedicated to 8019. They are not ne2k standard and are not commonly used, so they are not simulated. Our Register has three pages, with the page number 0-2. There are also two registers that do not belong to any page:

• 0x10 is the DMA read/write address, through which the CPU and network chip exchange data
• 0x1f is the reset address. Writing to or reading from this address causes reset of the network chip. Generally, the network chip is reset once during initialization, after resetting, wait for dozens of milliseconds before proceeding to the next step.

Table 0 1 8019as register

The following describes the registers on the pages simulated by the virtual 8019as network chip, as shown in table 0 1. For details about the bit meanings of each register, refer to the 8019as hardware specification manual. The following describes the offset addresses on the pages of each register and the meanings of common read/write values during driver writing, it is helpful for understanding. The write values of each register can be written after "or" relational operation. r indicates read-only, W indicates write-only, and R/W indicates read or write:

Page 0

• Cr control command registers: 0x00, R/W. The meaning of each bit in CR is as follows:
  Pai_stop 0x01 network chip stop sending and receiving data
  Pai_run 0x02 network chip executes the command and starts to send and receive packets (the command is the following four)
  Ipv_xmit 0x04 local DMA send (network chip-> Ethernet)
  Cmd_read 0x08 remote DMA read, used to manually receive data (network chip> CPU)
  Ipv_write 0x10 remote DMA write (network chip <-CPU)
  Pai_send 0x18 send command, used to automatically receive packets (network chip-> CPU)
  Cmd_nodma 0x20 stop the DMA Operation
  Cmd_page0 0x00 Select page 0th (select a page first and then read and write the Register on this page)
  Cmd_page1 0x40 select 1st page
  Pai_page2 0x80 select 2nd page
• Pstart: 0x01, W, receiving buffer ring start page
  Recv_start 0x4600 receiving buffer start address (8-bit right to get the page number when writing)
• Pstop: 0x02, W, receiving buffer ring termination page (excluding this page)
  Recv_stop 0x6000 receiving buffer end address (8-bit shifted to get the page number when writing)
• Bnry, 0x03, R/W, receive buffer ring read pointer
  During hardware initialization, pstart = curr. Then, use the pai_send command to automatically receive data packets. The network chip will automatically adjust the value of this register. If an error is received, it is adjusted to the value of curr.
• Tpsr, 0x04, W, local DMA sending buffer start page register.
  Xmit_start 0X4000 starting address of the sending buffer (the page number is obtained by shifting 8 digits to the right when writing)
• Tbcr0, 0x05, W, local DMA transmission length is low.
• Tbcr1, 0x06, W, local DMA transmission length is high.
  The above two registers are the length of outgoing packets from the network chip. They are set according to the actual length before executing the sending command.
• ISR, 0x07, R/W, interrupt Status Register. The meaning of each bit is as follows:
  Isr_prx 0x01 correctly receives data packet interruption. Receive
  Isr_ptx 0x02 correct packet sending interrupted. The upper-layer software should not be processed.
  An error occurred while receiving data packets in isr_rxe 0x04. Reset bnry = curr.
  An error occurred while sending isr_txe 0x08 because of the excessive number of conflicts. Re-sending
  Isr_ovw 0x10 network chip memory overflow. Restart the network chip for software processing. See the manual.
  Isr_cnt 0x20 the error counter is interrupted and shielded (IMR registers are blocked ).
  Isr_rdc 0x40 remote DMA ends. Block. Wait until the DMA ends.
  Isr_rst 0x80 network chip reset, shielded.

  Read the ISR register values in the interrupt processing program, respectively, with the preceding values "and". If the result is 1, this interrupt occurs and needs to be processed, after the process is completed, write this value to the ISR register (I .e., the interrupt location 1) to clear the interrupt.
  
  For example: if (ISR & isr_prx ){
  Process received packets;
  Iowrite (r_isr, isr_prx); clear the correct packet reception interruption
  };

• Rsar0, 0x08, W, remote DMA destination start address low
  Xmit_start 0X4000 takes its low position
• Rsar1, 0x09, W, remote DMA destination start address high
  Xmit_start 0X4000 takes its high position
• Low rbcr0, 0x0a, W, remote DMA data length
• High rbcr1, 0x0b, W, remote DMA data length
  The above two registers are the actual length of data packets written or read by the CPU to the network chip. You need to set these two registers before executing the remote DMA command.
• RCR, 0x0c, W, receiving configuration register,
  Write 0x04 during initialization, indicating that only Ethernet packets or broadcast packets larger than 64 bytes are received and sent to the MAC address of the network chip.
• CTL, 0x0d, W, Send configuration register
  Write 0x02 at the beginning of initialization, indicating that the network chip is set to loop back mode, stop sending data packets, and write 0x00 at the end of initialization. Send data packets normally with CRC added.
• DCR, 0x0e, W, Data configuration register
  Write 0x48 during initialization, which indicates the 8-Bit mode, the 8-byte FIFO depth, and the DMA mode.
• IMR, 0x0f, W, Interrupt Mask register
  All of them correspond to those in ISR. Writing the following values to IMR is to enable the corresponding interrupt,
  Isr_prx 0x01
  Isr_ptx 0x02
  Isr_rxe 0x04
  Isr_txe 0x08
  Isr_ovw 0x10
  Isr_cnt 0x20
  Isr_rdc 0x40
  Isr_rst 0x80
  For example, iowrite (r_imr, isr_ovw | isr_prx) indicates opening overflow and receiving interruption, and other interruptions are blocked.

Page 1:

• Cr: 0x00, R/W, which means the same as the Cr of page0.
• Par0, 0x01, R/W, maximum MAC address of the Network Chip
• Par1, 0x02, R/W, network chip MAC address
• Par2, 0x03, R/W, network chip MAC address
• Par3, 0x04, R/W, network chip MAC address
• Par4, 0x05, R/W, network chip MAC address
• Par5, 0x06, R/W, network chip MAC address rst bit
  If the MAC address of the network chip is: 00: 01: 02: 03: 04: 05, Pari = 0x0i. During initialization, the network chip reads the MAC address from the prom and writes it to these six registers.
• Curr, 0x07, R/W, receives the buffer ring write pointer, pointing to the start page when the next packet arrives.
  During hardware initialization, curr = bnry = pstart, which will be automatically updated by the network chip.
  In page1, the eight registers from 0x08 to 0x0 f are multicast address registers, which determine the network chip to send and receive multicast data packets and do not simulate these eight registers.

Page 2:

• Cr, 0x00, R/W, meaning the same as the Cr of page0
• Pstart, 0x01, R, used to read the pstart status
• Pstop, 0x02, R, used to read the pstop status
• Tpsr, 0x04, R, used to read the tpsr status
• RCR, 0x0c, R, used to read the receiving configuration register RCR status
• CRL, 0x0d, R, used to read and send the configuration register CTL status
• DCR, 0x0e, R, used to read data configuration register DCR status
• IMR, 0x0f, R, used to read the IMR status of the interrupt shield register

Most of the registers on this page are read-only and relevant configuration information can be read.

5. How the virtual network chip receives data packets

In the preceding Cr register description, we can see that there are two methods for reading data from the network chip RAM to the CPU:

1. Currently, the Skyeye virtual network chip does not support remote DMA read:
During hardware initialization, bnry read pointer = curr write pointer-1 = pstart.
To read data packets, follow these steps:

A. Check whether bnry is = curr-1. If it is not equal, data packets must be read.
B. Use bnry to initialize the DMA address controller rsar0, 1
C uses 18 to initialize the DMA length controller rbcr0, 1
D. Run the remote dma read command.
E. Read the Ethernet packet header (18 bytes) and read the packet length from the packet header.
F. Read all data from B-E.
G. Adjust bnry pointer = curr-1
During this period, if bnry refers to the tail of the buffer ring, it must be manually adjusted back to the beginning of the ring.

2. The virtual 8019 network chip supports a faster and simpler send command method. The steps for reading data packets are as follows:
During hardware initialization, bnry = curr = pstart
To read data packets, follow these steps:
A. Write 0fh to the rbcr1 register (required)
Iowrite (r_rbcr1, 0x0f );
B. Execute the send command
Iowrite (r_cr, pai_page0 | pai_send | pai_run)
Then the network chip automatically performs the following work:
I. Write the DMA controller (rsar0, 1) with the address pointed by the current bnry read pointer)
Ii. initialize the DMA controller (rbcr0, 1) with the packet length in the Ethernet header)
C. Read the 18-byte packet header to check whether the packet is valid.
D. read data from Port 0x10 ....... (Of course, you have to read the Ethernet packet header yourself)

6. skyeye_ne2k.c Function Description

• Nic_init: Call nic_reset to initialize the virtual network chip.
• Nic_reset: initializes various structures of the virtual 8019as, including registers, card prom, and ram.
• Nic_read: The read operation function of the network chip. The current value of the corresponding register is returned Based on the register offset given by the parameter. If the current value is 0x10, the DMA Input Function remote_read is called; if you are reading the 0x1f register, call nic_reset to restart the network chip.
  
• Nic_write: write operation function of the network chip. Modify the value of the corresponding register based on the register offset given by the parameter. If the value is 0x00 Cr, call write_cr to change the current status of the network chip; if the value is 0x10, call the DMA output function remote_write. If the value is 0x1 F, call nic_reset to restart the network chip.
  
• Tapif_input: Read the network package from the network interface of tapif and store it to the internal ram of the 8019as device (that is, the 8192-byte array ). Note that when RTL8019AS receives a network package, it will add four bytes at the top: 0x10, 0x50, and two bytes of package length to ensure full compatibility with the real 8019as network chip, skyeye's virtual 8019as network chip also simulates this feature. After the package transfer is completed, the tapif_input function modifies the interrupt Status Register of Skyeye and then returns the result. Skyeye enters the interrupt status next time it checks the interrupt Status Register.
  
• Tapif_output: This function is called by the packet sending function of the virtual 8019as network chip. It reads the network packet to be sent from the internal RAM of 8019as and forwards it to the tapif network chip interface.

7. Description of tapif and vnet Virtual Network Interfaces

The tun/TAP device and vnet device are Network Interface Devices (struct net_device) and are linked to the network interface linked list. Generally, it is created and registered in the tun_set_iff () function.

8. Network Chip Driver Analysis

Description of the DMA termination judgment when writing the driver CPU ---> the DMA termination mark of NIC's Ram is isr_rdc interrupt: While (char) (ioread (r_isr) & isr_rdc) = 0); here is the loop wait. If you do better, you can first return and wait for the end of the interrupt, which is generally unnecessary.

Nic 'ram ---> the DMA end mark of the network is isr_ptx interruption. If the upper-layer software still has packets to be sent continuously, you can enable the interrupt and continue sending the next packet in ISR. Otherwise, you do not need to handle the interrupt and can block it. (This is similar to the successful sending interruption of serial UART. If you want to send a string, use this interruption. It is unnecessary to send only one character .)

In Linux, The ne2k driver is also dead for a while. See the code in ne2k. C:

while ((inb_p(nic_base + EN0_ISR) & ENISR_RDC) == 0)if (jiffies - dma_start > 2*HZ/100) {/* 20ms */printk("%s: timeout waiting for Tx RDC.\n", dev->name);ne_reset_8390(dev);NS8390_init(dev,1);break;}