FPGA + CPU: popular in Parallel Processing

Two articles I accidentally saw in the morningArticleBecause the development of the next version of coolui is about to begin. In order not to be distracted, the blog will not be updated before the next version is completed, however, I really like this article-a new trend that is not noticed by us outside of sight;

In the era of deep sub-micron, traditional materials, structures, and even processes are moving towards extreme conditions, and Moore's Law is somewhat stretched. In the era of Deep Sub-Nano, the size of the transistor will be close to a single atom, and it cannot be further reduced. Traditional ASIC and ASSP designs inevitably encounter difficulties such as complicated design processes, reduced production yield, long design cycle, and sharp increase in R & D and manufacturing costs, to some extent, Moore's Law has slowed down.

Obviously, many small and medium-sized companies have to change their strategies and turn to FPGA development and design in the face of huge streaming costs. On the other hand, even five years ago, its market growth relative to ASIC was quite slow. However, in recent years, especially after entering the 90nm node, its cost advantage has gradually become prominent.

For more than two decades, Xilinx and Altera, the two giants that have long dominated the programmable logic device market, are still operating frequently. In August, The Altera seminar, a technology tour in 13 cities, pushed V series products on the 28nm process with great fanfare, the change of the new qsys platform from the FPGA builder to the soc fpga. In contrast, Xilinx in September is much more low-key, but still comes up with 7 series of products and competitors. From 65nm a year ago to 28nm today, because the door delay is no longer the bottleneck of speed and performance improvement, the changes that users can feel are only the increase in device density and the decrease in unit costs. In addition, it can only be said that the manufacturers have racked their brains to optimize the device architecture and improve the performance of development tools has become another landscape for viewing.

Coincidentally, Xilinx and Altera have accelerated the launch of FPGA Devices with embedded hard core CPUs. FPGA + CPU solution is not uncommon. It was proposed and put into practice five years ago. Xilinx and Altera have been committed to promoting their own soft-core CPU, however, the market response apparently failed to meet expectations. Xilinx was the first to integrate arm in last April to meet market requirements.
Cortex-A9 CPU and 28nm FPGA scalable processing platform (Extensible processingplatform) architecture. Less than a year later, the Zynq-7000 series of the scalable processing platform was moved to the front-end, Xilinx's painstaking efforts can be seen. Altera is not weak either. Intel integrated Altera's FPGA in the lingdong e600c configurable processor released last autumn, in addition, the soc fpga, which is also integrated with the Cortex-A9 CPU, which Altera will launch soon, is obviously playing against Xilinx.

For us, we need to explore and think about whether this new development platform meets the increasing "material culture" needs of our customers. We can't help wondering whether the FPGA + CPU integration architecture conforms to the historical development trend or is it just a flash in the eye?

1. A simplified traditional embedded system is shown in the left figure. The FPGA architecture with a single chip integrated with the CPU is shown in the right figure. From the perspective of hardware architecture alone, it seems that there is not much advantage, but only two in one. However, engineers who have actually done System Development know that this two-in-one solution not only simplifies BOM cost reduction and layout, more benefits are the optimization of underlying software and hardware connections that we cannot see with the naked eye, the flexibility in the invisible, and the potential performance improvement.

FPGA-based CPU integration will bring about some potential advantages, including: easier to meet the functional requirements of most systems; potential to improve system performance; in some applications, the flexibility and scalability are greatly improved; the interfaces from processors to peripherals can be optimized; the performance of software and hardware interconnection interfaces can be greatly improved; it is conducive to the reuse of design and the rapid prototyping of new designs; simplify the layout of a single chip or even the entire board.

The advantages of FPGA + CPU Single-chip integration compared with traditional applications can be seen, but from another perspective, as the evolution of CPU from single core to multi-core continues Moore's Law ", FPGA + CPU strength is more like parallel processing in embedded applications.

Continued consistent style, Xilinx and Altera in its embedded cpu fpga Devices are not the same with the choice of excellent performance of the arm Cortex-A9 kernel, it can be seen that they are currently targeting the market tends to be in the middle and high-end application customers. In terms of low-end applications, even in the era of network explosion, the obscure capital-micro companies are still not well known by engineers, but the reconfigurable system chip csoc developed by them) however, it has quietly shot a bloody path in low-end and Middle-end market applications. It is worth mentioning that this is a local FPGA manufacturer in China.

It has been 40 years since Intel's first 4-bit processor in 1971. Although the embedded industry has undergone dramatic changes, but even if you think it is "Earth to tooth" but simple and practical 8-bit MCS-51 SCM is still unique, especially in the domestic industrial control industry is still very strong vitality. Since its establishment in, capital-Micro has successively launched two generations of csoc: Astro and astroii. The embedded 8051 can run stably to 150 MHz and MHz on two generations of devices respectively. Although the FPGA manufacturing process is still 0.13um, it greatly limits the logic performance, however, the current two generations of products can at least meet the industrial application requirements including stepper motor control, LCD Drive Control, interface expansion, led control card, and micro printer.

From the perspective of the internal architecture of the device, as shown in figure 2, not only does astroii have 8051 hard core that is "superior" among similar products, it also integrates some common peripherals such as timer, watchdog, UART, IIC and SPI. Of course, the 8051ProgramThe startup also completely adopts a direct arm ing (fully shadowed) method similar to many arm to ensure that ROM with slow read/write is no longer a bottleneck restricting CPU performance. In terms of the interconnection between 8051 and FPGA, EMIF addressing (23-bit wide addressable Address Bus) can be used, 4 K × 8 bit DPRAM is also a good choice for high-speed data transmission, in addition, the synchronization logic has been fixed on these interconnected interfaces, eliminating the need for designers to waste energy. In addition, from the cheapest crystal clock support, to the maximum number of I/O, to its approachable price, it shows us the "economical application" of the Chinese chip ".

All in all, whether it's Xilinx, Altera, or capital-micro, they're pushing new monolithic integrated devices, it is predicted that the parallel processing architecture of FPGA + CPU will open up a new world in embedded applications. This single-chip performance improvement is about to enter the Extreme Deep Sub-Nano era, with its unique concurrency, the flexible and variable FPGA will surely help the performance of traditional CPU to reach a new level.

(From: http://www.ed-china.com/ART_8800043721_400005_500013_OT_4ec6fa87_02.HTM)