FPGA development of the eight: from the development of programmable devices to see the future trend of FPGA
FPGA development All the nine: FPGA main suppliers and products (1)
FPGA development All the nine: FPGA main suppliers and products (2)
FPGA development All the nine: FPGA main suppliers and products (3)
The development of programmable logic devices the development of programmable logic devices can be divided into 4 stages, that is, from the early 1970s to 70 the 1th paragraph, the mid 1970s to 80 to the 2nd stage, the 1980s to the late 90 3rd stage, The late 1990s to present is the 4th stage.
The 1th stage of programmable devices only simple programmable read-only memory (PROM), ultraviolet erasable read-only memory (EPROM) and electrically erasable read-only Memory (EEPROM) 3, due to the limitations of the structure, they can only complete simple digital logic functions.
In the 2nd stage, the structure of a slightly more complex programmable array logic (PAL) and universal Array logic (GAL) devices, formally known as PLD, is able to complete a variety of logical operation functions. The typical PLD is composed of "and", "non" array, with "and or" expression to implement any combination logic, so PLD can complete a large number of logical combinations in product and form.
The 3rd stage Xilinx and Altera respectively introduced the standard gate array similar to the FPGA and similar to the PAL structure of the extended CPLD, improve the speed of the logic, with the architecture and Logic unit flexible, high integration and wide range of application features, compatible with the advantages of PLD and Universal Gate Array, can achieve ultra-large-scale circuit, programming is also very flexible, become a product prototype design and small and medium-sized (generally less than 10000) product production preferred. At this stage, CPLD, FPGA devices in the manufacturing process and product performance have achieved considerable development, reached 0.18 process and coefficient gate millions of door size.
The 4th stage appeared sopc and SOC technology, which is the result of the fusion of PLD and ASIC technology, which covers the whole content of real-time digital signal processing technology, high-speed data transceiver, complex computing and embedded system design technology. Xilinx and Altera have also launched the corresponding SOCFPGA products, the manufacturing process reached 65nm, the number of systems more than million door. In this phase, the logic device incorporates a hard-core high-speed multiplier, a gbits differential serial interface, a powerpc™ microprocessor with a clock frequency of up to 500MHz, a soft core microblaze, Picoblaze, Nios, and Niosii, It not only realizes the perfect combination of software requirement and hardware design, but also realizes the perfect combination of high speed and flexibility, which has surpassed the performance and scale of ASIC device, also surpasses the concept of FPGA in the traditional sense, and makes the application range of PLD extend from monolithic to system level. In the future, Xilinx executives revealed that the company is developing new FPGAs using new processes that will integrate larger storage units and other functional devices, and FPGAs are moving in the direction of super-system chips! February 5, Xilinx released the 40nm and 45nm Spartan-6 and Virtex-6 FPGA series, and opened the target design platform This new design concept, I believe that the application of FPGA will be more development!
In 1984, Xilinx invented the field Programmable gate Array (FPGA), and it became the first fabless semiconductor company in the world, Xilinx through the continuous application of cutting-edge technology to maintain its industry leader for a long time: Xilinx is the first to use 180nm, 150nm, 130nm, 90nm and 65nm process technology companies, currently providing about 90% of the world's high-end 65nm FPGA products. According to ISuppli's statistics, it has a market share of more than 51% of the world's programmable devices over 2007 years. Currently, the main suppliers of FPGA are Xilinx, Altera, Actel and lattice. Among them Altera and Xilinx mainly produce the general purpose FPGA, its main product uses the RAM craft. Actel mainly provides non-volatile FPGA, the product is mainly based on the anti-fuse process and flash process.
As Xilinx has a leading edge and largest share in FPGA development, this article mainly introduces Xilinx's FPGA products.
3.1.1 Xilinx Main product Introduction
At present, Xilinx has two major types of FPGA products: Spartan class and Virtex class, the former mainly for low-cost mid-low-end applications, is currently the industry's lowest cost of a class of FPGA, the latter mainly for high-end applications, belongs to the industry's top products. The differences in these two series are limited to the size of the chip and the dedicated modules, all using advanced 0.13, 90 or even 65 manufacturing processes, with the same excellent quality.
1. Spartan class FPGA
The Spartan series is suitable for general industrial, commercial and other fields, the current mainstream chips include: Spartan-2, spartan-2e, Spartan-3, spartan-3a, spartan-3e and the latest Spartan-6 and other categories. Among them Spartan-2 up to 200,000 system gates, spartan-2e up to 600,000 system gates, Spartan-3 up to 5 million doors, spartan-3a and spartan-3e not only the system door number larger, It also enhances a large number of embedded dedicated multipliers and dedicated block RAM resources, with the ability to implement complex digital signal processing and on-chip programmable systems.
(1) Spartan-2 Series
Based on the Spartan series, Spartan-2 has inherited more logical resources to achieve higher performance with a chip density of up to 200,000 system gates. Due to the use of a mature FPGA structure, support popular interface standards, with an appropriate amount of logical resources and on-chip RAM, and provide flexible clock processing, can run 8-bit Picoblaze soft core, mainly used in various low-end products. The main features are as follows: Using 0.18 process, the density reaches 5292 logic units, the system clock can reach 200MHz, the maximum number of doors is 200,000, with the delay digital phase-locked loop, programmable user I/O, with on-chip RAM storage resources;
The main technical features of the Spartan-2 series are shown in the table below.
Table 3-1 Spartan-2 Series FPGA main technical features
(2) SPARTAN-2E Series
The spartan-2e is based on the VIREX-E architecture and has more logic gates, user I/O, and higher performance than Spartan-2. Xilinx also provides IP cores including memory controller, System interface, DSP, communication and network, and can run CPU soft core, which has some support for DSP. Its main features are as follows: The 0.15 process, the density of 15552 logic units, the maximum system clock can reach 200MHz, the gate number is 600,000 doors, up to 4 time-delay phase-locked loop; nuclear power 1.2v,i/q voltage can be 1.2V, 3.3V, 2.5V, support 19 optional I /o Standard, up to 288k block RAM and 221K of distributed ram;
The main technical features of the SPARTAN-2E series are shown in the table below.
Table 3-2 SPARTAN-2E Series FPGA main technical features
(3) Spartan-3 Series
The Spartan-3 is based on the Virtex-ii FPGA architecture, with 90 technology, 8 layers of metal process, more than 5 million system gates, embedded with a hard multiplier and digital clock management module. Structurally, Spartan-3 combines logic, memory, mathematical operations, digital processor, I/O, and system management resources together to make it a higher-level, wider application, gaining commercial success and occupying a larger share of the mid-low market. Its main characteristics are as follows: Using 90 process, density up to 74880 logic units, maximum system clock is 340MHz, with special multiplier, nuclear power pressure 1.2V, port voltage 3.3V, 2.5V, 1.2V, support 24 I/O Standard , up to 520k of distributed ram and 1872k of Block RAM, with on-chip clock Management module (DCM), with embedded Xtrema DSP function, can perform 330 billion times per second multiply plus.
The main technical features of the SPARTAN-3 series are shown in the table below.
Table 3-3 Spartan-3 Series FPGA main technical features
(4) Spartan-3a/3adsp/3an Series
Based on the Spartan-3 and spartan-3e platforms, SPARTAN-3A integrates innovative features to help customers greatly reduce the total cost of the system. Achieve the industry's first FPGA electronic serial number with unique device DNA ID technology, providing an economical, powerful mechanism to prevent tampering, cloning, and over-design. Enhanced multi-boot feature with integrated watchdog monitoring. Supports commercial lash memory, helping to reduce total system cost. Its main characteristics are: Using 90 process, density up to 74880 logic units, the working clock range is 5mhz~320mhz; the leading connectivity platform with the widest IO standard (26 types, including new TMDS and PPDS) support; unique Device The industry's first powerful anti-cloning security feature in the DNA serial number, five devices with system gates up to 1.4M and 502 I/O, and flexible power management.
The main technical features of the SPARTAN-3A series are shown in the table below.
Table 3-4 SPARTAN-3A Series FPGA main technical features
The SPARTAN-3ADSP platform offers the most cost-effective DSP devices, the core of which is the XTREMEDSP dsp48a slice, and provides a new type of performance over 30gmac/s, memory bandwidth up to 2196 Mbps xc3sd3400a and xc3sd1800a devices. The new SPARTAN-3A DSP platform is ideal for cost-sensitive DSP algorithms and co-processing applications that require very high DSP performance. The main features are shown below. Using 90 process, the density is up to 74880 logic units, the embedded dsp48a can work to 250MHz, and a structured Selectram architecture provides a large number of on-chip storage units; The Vccaux voltage supports 2.5V and 3.3V, simplifies design for 3.3V applications, and low power efficiency, SPARTAN-3A DSP devices have a high signal processing capability 4.06 GMACS/MW.
The main technical features of the SPARTAN-3ADSP series are shown in the table below.
Table 3-5 SPARTAN-3ADSP Series FPGA main technical features
The Spartan-3an chip is a non-volatile security FPGA with the highest level of system integration, offering the following 2 unique features: The high performance of advanced SRAM FPGAs and the security of non-volatile FPGAs, saving board space, and easy-to-configure features. The Spartan-3an platform is ideal for space-demanding and/or secure applications and low-cost embedded controllers. Key features of the Spartan-3an platform include the industry's first 90nm non-volatile FPGA, a device DNA electronic serial number that enables flexible, low-cost security, the industry's largest on-chip user flash, and the broadest range of I/O standards support, Includes 26 single-ended and differential signal standard flexible power management modes, saving over 40% power consumption in sleep mode with five devices with up to 1.4M system doors and 502 I/O.
The main technical features of the Spartan-3an series are shown in the table below
Table 3-6 Spartan-3an Series FPGA main technical features
(5) SPARTAN-3E Series
SPARTAN-3E is currently the latest Spartan series products, with a number of system door from 100,000 to 1.6 million of a variety of chips, is in
Spartan-3 success based on further improvement of the product, provides more I/O ports and lower unit costs than Spartan-3, is Sailing
The most cost-effective FPGA chip in the company. By making better use of the 90 technology, more functionality and processing bandwidth are achieved on a per unit cost, which is
Xilinx's new low-cost product representation is an effective alternative to ASIC, primarily for consumer electronics applications such as broadband wireless access, home networking
and digital TV devices. Its main features are as follows: using 90 process; Large number of user I/O ports, up to 376 I/O ports supported
or 156 pairs of differential ports, the port voltage is 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, the single-ended port can transmit the rate of 622, support
With a DDR interface, up to 36 dedicated multipliers, 648 RAM, 231 distributed RAM, wide clock frequency, and multiple dedicated slices
On the digital Clock Management (DCM) module.
The main technical features of the SPARTAN-3E series are shown in the table below.
Table 3-7 spartan-3e Series FPGA main technical features
Table 3-8 spartan-3a Extension Series performance comparison
(6) SPARTAN-6 Series
As the sixth generation of the Spartan FPGA series, the Spartan-6 FPGA series is manufactured using a reliable, low-power, 45nm, 9-layer, metal-routed double oxidation process. This new family of products achieves a perfect balance of low risk, low cost, low power consumption and high performance. The Spartan-6 FPGA family's efficient dual-register 6 input LUT (lookup table) logical structure leverages a robust, proven Virtex architecture that supports cross-platform compatibility and optimizes system performance. The rich built-in system-level modules include DSP logic slices, high-speed transceivers, and PCI express® interface cores, as well as the Virtex series, to provide a higher degree of system-level integration.
The Spartan-6 FPGA family uses special technologies for cost and power-sensitive markets such as automotive entertainment, flat panel display, and video surveillance. The new high-performance integrated memory controller supports DDR, DDR2, DDR3, and mobile DDR memory, and the hard-core multi-port bus architecture provides predictable timing and performance up to DDR2/DDR3 (400MHz). With the support of the Design wizard, the process of building a storage controller for the Spartan-6 FPGA becomes very simple and straightforward.
Innovations in advanced power management technology and an optional 1.0v low-power core enable the Spartan-6 FPGA to reduce power consumption by up to 65% over the previous generation Spartan series. Fast and flexible I/O supports over 12Gbps of memory access bandwidth, compatible with 3.3v voltages and a greener RoHS-compliant lead-free package.
The main technical features of the SPARTAN-6 series are shown in the following table:
Table 3-9 Spartan-6 Series FPGA main technical features
2.Virtex Series FPGA
Virtex series is Xilinx's high-end products, but also the industry's top FPGA products, Xilinx company is relying on Virtex series products to win the market, so as to obtain the status of FPGA supplier leader. It can be said that Xilinx with its Virtex-5, Virtex-4, Virtex-2 Pro and Virtex-2 series FPGA products lead the field programmable gate array industry. Mainly for telecommunications infrastructure, automotive industry, high-end consumer electronics and other applications. Current mainstream chips include: Vitrex-2, Virtex-2 Pro, Virtex-4 and Virtex-5, among other categories.
(1) Vitrex-2 Series
The Vitrex-2 series offers excellent platform solutions that further enhance its performance, and the built-in IP core hard core technology allows hard IP cores to be allocated anywhere on the chip, with more resources and higher performance than the Virtex series. Its main characteristics are as follows: using 0.15/0.12 process, nuclear power pressure of 1.5V, the working clock can reach 420MHz, support more than 20 kinds of I/O interface standard, embedded several hard multiplier, improve DSP processing power, with complete system clock management function, up to 12 DCM modules.
The main technical features of the VIRTEX-2 series are shown in the table below.
Table 3-10 Virtex-2 Series FPGA main technical features
(2) Virtex-2pro Series
The Virtex-2 Pro Series, based on Virtex-2, enhances the embedded processing capabilities, incorporates the powerpc™405 core, and includes advanced active interconnect (active interconnect) technology to address the challenges of high-performance systems. In addition, high-speed serial transceivers are added, providing a Gigabit Ethernet solution. Its main characteristics are as follows: using 0.13 process, nuclear power pressure 1.5V, the working clock can reach 420MHz, support 20 kinds of I/O interface standards, add 2 high-performance RISC technology, frequency up to 400MHz powerpc™ processor , Rocket serial transceiver with multiple 3.125Gbps speeds, multiple hard-core multipliers embedded, improved DSP processing power, complete system clock management, up to 12 DCM modules.
The main technical features of the Virtex-2 Pro Series are shown in the table below.
Table 3-11 Virtex-2 Pro Series FPGA main technical features
(3) VIRTEX-4 Series
The VIRTEX-4 device incorporates up to 200,000 logic units, up to a performance of up to a maximum of MHz and unmatched system features. Based on the new Advanced Silicon Module (ASMBL) architecture, the VIRTEX-4 product offers a multi-platform approach (LX, SX, FX) that allows designers to select different development platforms based on their needs, high logic density, 500MHz clock frequency, DCM modules, PMCD phase Matching clock divider, on-chip differential clock network, 500MHZ Smartram technology with integrated FIFO control logic, each I/O integrates 1 Gbps I/O and Xtreme DSP logic slices for Chipsync source synchronization technology. The main features are as follows: 90 process, integrated logic unit up to 200,000, system clock 500MHz, 500MHz Smart RAM technology with integrated FIFO control logic, DCM module, PMCD phase matching clock divider and on-chip differential clock network; each i/ O are integrated with the 1Gbps I/O of the Chipsync source synchronization technology, with superior signal processing capability, with the integration of hundreds of XTREMEDSP Slice, the single-chip maximum processing rate. The Virtex-4 LX platform FPGA is characterized by a density of up to 200,000 logic units, one of the world's most logically dense FPGA families, and is suitable for design applications with high logic gate requirements.
The Virtex-4 SX platform increases the ratio of DSP, Ram unit to logic unit, can provide up to 512 XTREMEDSP hard cores, can operate at 500MHz, its maximum processing rate is, and can create more than 40 different functions, More large-scale DSP modules can be implemented in multiple combinations. The cost and power consumption are significantly reduced compared to the Virtex-2 Pro Series, with very low DSP costs. The FPGA on the SX platform is ideal for high-speed, real-time digital signal processing applications.
The Virtex-4 FX platform incorporates one or two 32-bit RISC powerpc™ processors, providing 4 1300 dhrystone MIPS, A/X adaptive Ethernet Mac Core, and a coprocessor controller unit (APU) Allows the processor to construct special instructions in the FPGA, so that the performance of the FX device is 20 times times the fixed instruction mode, and also includes 24 rocket I/O serial high-speed transceivers, supporting common 0.6Gbps, 1.25 Gbps, 2.5 Gbps, 3.125 Gbps, 4 Gbps , 6.25 Gbps, and ten Gbps high-speed transmission rates. The FX platform is ideal for complex computing and embedded processing applications.
The main technical features of the VIRTEX-4 series are shown in the table below.
Table 3-12 Virtex-4 Series FPGA main technical features
Table 3-13 Virtex-4 Series platform Performance comparison
(5) VIRTEX-5 Series
The Virtex®-5 FPGA is the world's first 65nm FPGA family, manufactured using 1.0v, Tri-gate oxide technology, and offers 330,000 logic units, 1,200 I/O pins, 48 low power transceivers, and built-in PowerPC based on the selected device. ™440, PCIe® endpoint, and Ethernet MAC module. There are 5 series of platforms, LX, LXT, SXT, FXT, TXT, each of which provides the best balance in high-performance logic, serial connectivity, signal processing, and embedded processing performance. For example, LX is optimized for high-performance logic, and the LXT is optimized for high-performance logic with low-power serial connectivity, and is optimized for DSP and memory-intensive applications with low-power serial connectivity capabilities. SXT The Virtex-5 FXT is used for embedded processing with the highest rate of serial connectivity, and VIRTEX-5 txt can be used for ultra-high bandwidth applications such as bridging, switching, and clustering within a wired communication and data communication system.
The main technical characteristics of the existing VIRTEX-5 series products are shown in the table below.
Table 3-14 Virtex-5 Series FPGA main technical features
Its main features are as follows:
Using the latest 65 process, combined with a low-power IP block to reduce dynamic power consumption by 35%, and the use of 65nm three-gate oxide layer technology to maintain low quiescent power consumption, the use of 65nm expressfabric technology, the realization of a true 6 input lut, and improve performance of 2 speed levels. The enhanced Kbit Block RAM with built-in FIFO logic and ECC for larger arrays has a low-power circuit to shut down unused memory. Up to 330,000 logic units for unmatched performance, up to 1,200 I/O pins, high bandwidth memory/network interface, 1.25 Gbps LVDS, up to 24 low power transceivers, and up to Mbps-3.75 Gbps high-speed serial interface; Nuclear power pressure is 1v,550 MHz system clock, 550 MHz dsp48e Slice built-in X-MAC, provides 352 gmacs performance, able to reduce resource utilization by 50%, to achieve single-precision floating point operations; Increase area efficiency with built-in PCIe endpoints and Ethernet MAC modules; a more flexible clock management pipeline (Clock Management Tile) combines a new PLL for precise clock phase control with jitter filtering and a digital clock manager (DCM) for a variety of clock synthesis; The second-generation sparse chevron package improves signal integrity and lowers system costs, increases device configuration, supports commercial flash memory, and lowers costs.
Note: A Virtex-5 slice has 4 lut and 4 triggers, whereas a conventional slice mentioned earlier contains only 2 Lut 2 triggers. Each dsp48e contains a 25*18 bit of a hard multiplier, an adder, and an accumulator.
Virtex-5 FPGA ordering information for all packages, including lead-free packages
(6) Virtex-6 FPGA series
Based on the 40nm manufacturing process using the third-generation Xilinx asmbl™ architecture, the Virtex-6 FPGA family also has a new generation of development tools and extensive IP library support already developed for Virtex-5 FPGAs. These provide strong support for prolific development and design porting. The new Virtex-6 FPGA family features a 15% increase in performance and a 15% reduction in power consumption compared to 40nm FPGA products from competitors. The new device operates on a 1.0v core voltage and also has an optional 0.9v low power version. This enables system designers to use Virtex-6 FPGAs in their designs to support the construction of "green" central offices and data centers. This is particularly important for the telecommunications industry, which is expanding support for Internet video and rich media content.
The Virtex-6 FPGA family includes three application-oriented FPGA platforms optimized to provide different features and functional combinations to better meet the needs of different customer applications:
Virtex-6 LXT fpga-optimized target applications require high-performance logic, DSP, and serial connectivity based on a low power GTX 6.5Gbps serial transceiver.
Virtex-6 SXT fpga-optimized target applications require ultra-high performance DSP and serial connectivity capabilities based on the low power GTX 6.5Gbps serial transceiver.
The Virtex-6 HXT fpga-as an optimized communication application requires the highest serial connectivity capability, and up to 64 gth serial transceivers provide up to 11.2Gbps bandwidth.
Virtex-6 FPGAs combine advanced hardware chip technology, innovative circuit design technology, and architectural enhancements to significantly reduce power consumption, performance, and cost compared to previous generation Virtex devices and competing FPGA products. Table 3-15 shows the main technical features of the VIRTEX-6FPGA series.
Table 3-15 Virtex-6 FPGA series main technical features
(7) Xilinx Prom Chip Introduction
Xilinx's platform Flash Prom provides non-volatile storage for all models of Xilinx FPGAs. The full range of prom capacities ranges from 1Mbit to 32Mbit and is compatible with any Xilinx FPGA chip with full industrial temperature characteristics (-40°c to + 85°c) and supports the JTAG Boundary Scan protocol defined by IEEE1149.1.
Prom chip can be divided into 3.3V nuclear power series and 1.8V nuclear power series two categories, the former mainly for the bottom reference, serial transmission of data, and small capacity, does not have the function of data compression, the latter mainly for high-end FPGA chip, support parallel configuration, design revision (designing revisioning) and advanced features such as data compression (Compression) are known for their high capacity and speed, with detailed parameters shown in the table below.
Table 3-16 Turing's Prom chip summary (as of November 2008 data)
The series includes xcf01s, xcf02s and xcf04s (capacity: 1Mb, 2Mb, and 4Mb) and features a common feature of 3.3V nuclear power, a serial configuration interface, and a VO20 package in the Soic package. The overall structure of the internal control signal, data signal, clock signal, and JTAG signal is shown in 3-2.
Figure 3-2 xcf01s/xcf02s/xcf04s Prom structure block diagram
The series has xcp08p, xcf16p and xcf32p (capacity: 8Mb, 16Mb, and 32Mb) with common features such as 1.8V nuclear power, serial or parallel configuration interfaces, design revisions, inline data compressors, FS48 packages or VQ48 packages, and inline oscillators. The overall structure of the internal control signal, data signal, clock signal, and JTAG signal is shown in 3-3, and its advanced structure and higher integration provide great flexibility in use.
Figure 3-3 xcp08p/xcf16p/xcf32p Prom structure block diagram
Worth mentioning is the series of design correction and data compression two features. The design revision feature changes the configuration data at FPGA power-on startup, changes the functionality of the FPGA as needed, allows users to store multiple configurations as different revisions in a single prom, simplifies FPGA configuration changes, and adds a small amount of logic inside the FPGA Users can store dynamic transitions between up to 4 different revisions in a prom. The data compression feature saves prom space, saves up to 50% of storage space, and reduces costs, which is a very practical technique. Of course, if the programming in the software side of the compression mode, you need a certain hardware configuration to complete the corresponding decompression.
FPGA development All-in---FPGA development and Xilinx series