FPGA development All-in---FPGA internal structure

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FPGA development All-in-five: FPGA main Function Module introduction (1)

FPGA development of the six: Digital clock management module and embedded block RAM

FPGA development of the seven: the bottom embedded functional units and soft core, hard core and solid core

1. Programmable input/output unit (IOB)

The programmable input/output unit is referred to as the I/O unit, which is the interface part of the chip and the external circuit, and the driving and matching requirements for the input/output signal under different electrical characteristics are shown in the schematic structure 2-4. The I/O in the FPGA is categorized by group and each group is able to independently support different I/O standards. Flexible configuration of the software can be adapted to different electrical standards and I/O physical characteristics, can adjust the size of the drive current, can change the upper and lower pull resistance. At present, I/O port frequency is also increasing, some high-end FPGA through the DDR register technology can support up to 2Gbps data rate.

Figure 2-4 IOB Internal structure
The external input signal can be input to the inside of the FPGA via the storage unit of the IOB module or directly inside the FPGA. When an external input signal passes through the IOB module's storage unit into the FPGA, its hold time requirement can be reduced, usually by default of 0. In order to facilitate the management and adaptation of a variety of electrical standards, FPGA IOB is divided into several groups (banks), each bank interface standard is determined by its interface voltage Vcco, a bank can have only one vcco, but different bank Vcco can be different. Only ports of the same electrical standard can be connected together, the same VCCO voltage is the basic condition of the interface standard.

2. Configurable logical blocks (CLB

CLB is the basic logical unit within the FPGA. The actual number and characteristics of CLB vary depending on the device, but each CLB contains a configurable switch matrix consisting of 4 or 6 inputs, some selector circuits (multiplexers, etc.) and triggers. The switch matrix is highly flexible and can be configured to handle combinatorial logic, shift registers, or RAM. In the FPGA devices of the company, the CLB consists of multiple (typically 4 or 2) identical slice and additional logic, as shown in 2-5. Each CLB module can be used not only for the implementation of combinatorial logic, timing logic, but also for distributed RAM and distributed ROM.

Figure 2-5 A typical CLB structure
Slice is the basic logical unit defined by Xilinx Corporation, with its internal structure of 2-6, a Slice consisting of two 4 input functions, carry logic, arithmetic logic, storage logic, and function multiplexer.

Figure 2-6 Typical 4 input slice structure
The arithmetic logic consists of an XOR gate (XORG) and a dedicated with the gate (Multand), an XOR gate that enables a slice to implement a full 2bit operation, dedicated with the door to improve the efficiency of the multiplier; The carry logic consists of a dedicated carry signal and a function multiplexer (MUXC), For fast arithmetic addition and subtraction operations; the 4 input function generator is used to implement a 4 input lut, distributed RAM, or 16-bit shift register (two input functions in the slice of the VIRTEX-5 series chip are 6 inputs, can implement 6 input LUT or 64-bit shift registers); rounding logic includes Two fast carry chains to improve the processing speed of the CLB module.

3. Digital Clock Management module (DCM)

Digital clock management is available in most FPGAs in the industry (all of Xilinx's FPGAs have this feature). Xilinx launches state-of-the-art FPGAs that provide digital clock management and phase loop locking. Phase loop locking provides precise clock synthesis, reduces jitter, and enables filtering functions.

4. Embedded block Ram (BRAM)

Most FPGAs have embedded block RAM, which greatly expands the scope and flexibility of FPGA applications. Block RAM can be configured as a common storage structure such as single-port RAM, dual-port RAM, content address memory (CAM), and FIFO. RAM, FIFO is the concept of more popular, here is not redundant. The cam memory has a comparative logic in each memory unit inside it, and the data written into the cam is compared to each of the internal data and returns the address of all the data that is the same as the port data, so it is widely used in the routed address switch. In addition to block RAM, the LUT in the FPGA can be flexibly configured into structures such as RAM, ROM, and FIFO. In practical applications, the number of block RAM inside the chip is also an important factor in the selection of chips.

Figure 2-7 Embedded Block Ram

The capacity of the monolithic block RAM is 18k bit, the accession width is 18 bit, the depth is 1024, can change its bit width and depth according to need, but satisfies two principle: first, the modified capacity (bit width depth) cannot be greater than 18k bit, secondly, the maximum bit width cannot exceed 36 bits. Of course, multiple pieces of RAM can be cascaded together to form larger amounts of RAM, which is limited by the number of block RAM in the chip, and is no longer constrained by the two principles above.

5. Rich Cabling Resources

The cabling resource connects all the elements inside the FPGA, and the length and process of the wire determine the drive and transmission speed of the signal on the wire. The FPGA chip has a wealth of cabling resources, divided into 4 categories according to the process, length, width and distribution of different locations. The first category is the global cabling resources, for the chip internal global clock and global reset/set the wiring; the second is a long-term resource to complete the high-speed signal between the chip bank and the second global clock signal wiring; The third category is short-term resources for logical interconnection and cabling between basic logical units. The fourth category is distributed cabling resources for proprietary clocks, resets, and other control signal lines.

Figure 2-8 FPGA internal interconnect cabling

In practice, designers do not need to directly select the cabling resources, the layout of the router can automatically according to the Input Logical network table topology and constraints to select the routing resources to connect the module units. In essence, the use of cabling resources and design results have a close, direct relationship.

6, the bottom embedded function unit

The embedded function module mainly refers to the DLL (Delay Locked loop), the PLL (Phase Locked Loop), the DSP and other soft processing cores (Soft core). Now more and more rich embedded function unit, make monolithic FPGA become system level design tool, make it have the ability of hardware and software joint design, transition to SOC platform gradually.

DLLs and PLLs have similar capabilities to complete clock high-precision, low-jitter multiplier and crossover, and duty-ratio adjustment and shift-equal functionality. Xilinx's chip integrated with DCM and Dll,altera Company's chip integrates the Pll,lattice company's new chip with integrated PLLs and DLLs. PLLs and DLLs can be easily managed and configured through the IP core-generated tools. The structure of the DLL is shown in 2-8.

Figure 2-9 Typical DLL modules

7. Embedded dedicated Hard Core

Embedded dedicated hard core is relative to the underlying embedded soft core, refers to the FPGA processing power of the hard core, equivalent to the ASIC circuit. To improve FPGA performance, chip manufacturers have integrated a number of dedicated hard cores inside the chip. For example: In order to improve the multiplication speed of FPGA, the main FPGA is integrated with special multipliers, in order to apply the communication bus and interface standards, many high-end FPGA internal integrated serial and transceiver (SERDES), can achieve dozens of Gbps transceiver speed.

Xilinx's high-end products not only integrate the power PC family of CPUs, but also embed the DSP Core module, the corresponding system-level design tools are EDK and platform Studio, and based on the concept of on-chip systems (System on chip). Through powerpc™, Miroblaze, Picoblaze and other platforms, the standard DSP processor and its related applications can be developed to achieve the purpose of SOC development.

In addition, the new Xilinx FPGA series such as Virtex-5 LXT also built a PCI Express and tri-State Ethernet Mac Hard Core (TEMAC), compared with the soft core implementation mode, the hard core can reduce power consumption 5~10 times, saving nearly 90% of the logical resources.

The Xilinx Tri-State Ethernet Mac Core is a parametric kernel that is ideal for use in network devices such as switches and routers. The customizable Temac core enables system designers to achieve a wide range of integrated Ethernet designs, from low-cost 10/100 Ethernet to higher-performance 1GB ports. The TEMAC core design complies with the requirements of the IEEE 802.3 specification and can operate in 1000Mbps, Mbps and Mbps modes.

In addition, it supports half-duplex and full-duplex operations. The Temac core is provided through the Xilinx core generator™ tool and is the Xilinx full Ethernet
Part of the network solution.

2.1.3 The concept of soft core, hard core and solid core

The IP (Intelligent property) core is an integrated circuit core of the IP core, is a repeatedly validated macro module with specific functions, independent of the chip manufacturing process, can be transplanted into different semiconductor processes. At the SOC stage, IP core design has become an important task of ASIC circuit design company and FPGA provider, and it is also the embodiment of its strength. For FPGA development software, the more IP cores it provides, the more convenient the user's design is, and the higher the market occupancy rate. At present, the IP core has become the basic unit of system design and has been exchanged, transferred and sold as an independent design result.
From the way the IP core is provided, it is usually divided into 3 categories: soft core, solid core and hard core. The hard core costs most from the cost of completing the IP core, and the reusable usability of the soft core is the highest in terms of flexibility of use.

1. Soft core (Soft IP Core)

The soft core in EDA design refers to the pre-integrated register transfer level (RTL) model, in which the hardware language of the circuit is described in the FPGA design, including the logical description, the Web table and the help document. The soft core is only function-simulated and needs to be integrated and layout-routed to be used. Its advantages are high flexibility and portability, allowing users to self-configure, the disadvantage is that the prediction of the module is low, in the subsequent design there is the possibility of error, there is a certain design risk. Soft core is the most widely used form of IP core.

2. Solid core (Firm IP Core)

In the field of EDA design, solid core refers to a network table with planar planning information, which can be seen in FPGA design as a soft core with layout planning, usually in the form of RTL code and a mixture of specific process Web tables. The RTL description is combined with a specific standard cell library for comprehensive optimization design, to form a gate-level grid, and then through the layout of the tool can be used. Compared with the soft core, the design flexibility of the solid core is slightly worse, but the reliability is greatly improved. At present, solid Core is also one of the mainstream forms of IP core.

3. Hard core (rigid IP core)

Hard core in the field of EDA design refers to a verified design layout, specifically in the FPGA design of the layout and process fixed, through the front-end and the backend validation of the design, designers can not modify it. There are two reasons why it cannot be modified: first, the system design has strict timing requirements for each module, does not allow the disruption of the existing physical layout, and the second is the requirement to protect intellectual property, and does not allow designers to change it. IP hard-to-modify features make it difficult to reuse, so it can only be used for certain applications with a narrower scope.

FPGA development All-in---FPGA internal structure