FPGA development--configuration circuit

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FPGA Development 12: FPGA Practical Development Skills (9)

FPGA Development 12: FPGA Practical Development Skills (10)

FPGA Development 13: FPGA Practical Development Skills (11)

5.5 FPGA-related circuit design knowledge

The relevant circuit of FPGA is mainly FPGA configuration circuit, the rest of the application circuit as long as the peripheral chip connected to the FPGA general-purpose I/O pin can be.

5.5.1 Configuration Circuit

The FPGA configuration method is flexible and diverse, depending on whether the chip can actively load the configuration data into the main mode, slave mode and JTAG mode. The typical main mode is the configuration bitstream in the non-volatile (power-not-lost) memory that is loaded on-chip, and the desired clock signal (called CCLK) is generated internally by the FPGA, and the FPGA controls the entire configuration process. The biggest advantage of downloading data from an external master intelligent terminal (such as a processor, microcontroller, or DSP) to an FPGA is that the FPGA configuration data can be placed on any storage part of the system, including: Flash, hard disk, network, and even in the running code of the remaining processors. JTAG mode is debug mode, the bit files in the PC can be streamed to the FPGA, the power loss is lost. In addition, Xilinx currently has an Internet-based, mature reconfigurable Logic Technology system ACE solution.

(1) Main mode

In the main mode, the FPGA automatically reads the configuration data from the corresponding external memory into the SRAM, realizes the internal structure mapping, and the main mode can be divided into two categories: Serial mode (single-bit stream) and parallel mode (byte-width bit-stream) according to the bit-width of the bit-stream. such as: main serial mode, main SPI Flash serial mode, internal main SPI Flash serial mode, master BPI parallel mode, and main parallel mode, 5-19 shown.

(2) from the mode

In slave mode, the FPGA is used as slave device, and the corresponding control circuit or microprocessor provides the timing required for configuration, and the download of configuration data is realized. From the pattern also according to the bit width of the bit stream is divided into string, and pattern two categories, including: From the serial mode, JTAG mode and from the parallel mode of three categories, which is shown in the outline 5-20.

(3) JTAG mode

In Jtag mode, the PC and FPGA communication clock is the TCLK of the Jtag interface, and the data is directly from the TDI into the FPGA to complete the corresponding function configuration.

Figure 5-19 Common main Mode download method

Figure 5-20 commonly used download mode from the schema

At present, the mainstream FPGA chips support a variety of commonly used master, slave configuration mode and JTAG, to reduce the configuration circuit mismatch on the overall system impact. In the master configuration mode, the FPGA generates its own clock and loads the configuration data from the external memory, which can be either single-bit or byte-wide, and in slave mode, the external processor sends the configuration data to the FPGA chip in bits or bytes width by synchronizing the serial interface. In addition, multi-chip FPGAs can share the same block of external memory through the JTAG Daisy chain, and the same piece/multi-chip FPGA can read configuration data and user-defined data from multiple external memory.

The common configuration modes for Xilinx FPGAs are 5 classes: main string mode, slave string mode, Select map mode, desktop configuration, and direct SPI configuration. In a string configuration, the FPGA receives configuration bit data from the external prom or other device, which is configured with the clock CCLK generated by the FPGA, and multiple FPGAs can form a daisy chain to fetch data from the same configuration source. The configuration data in Select map mode is parallel and is the fastest configuration mode. The SPI configuration is primarily used in flash circuits with SPI interfaces. The following is an example of the SPARTAN-3E series of chips, giving the configuration circuit of various modes.

5.5.2 Main String mode-the most common FPGA configuration mode

1. Configuring a monolithic FPGA

In the main string mode, the CCLK pin of the FPGA provides a working clock to the prom, and the corresponding prom sends the data from the D0 pin to the din pin of the FPGA on the rising edge of the CCLK. Regardless of the prom chip type (even if it supports parallel configuration), only its serial configuration feature is used. The monolithic main string configuration circuit 5-21 of the SPARTAN3E series FPGA is shown. The main string mode is the simplest and most commonly used method of Xilinx's various configuration methods, and all of the basic programmable chips support the main string mode.

Figure 5-21 spartan-3e Main string mode configuration circuit

2. Configure the key points of the circuit

The key 3 points of the main string configuration circuit are the integrity of the JTAG chain, the setting of the supply voltage, and the consideration of the CCLK signal. The prom chip is not properly configured as long as there is a problem with any of these 3 steps.

(1) The integrity of the JTAG chain

Both the FPGA and prom chips have their own JTAG interface circuitry, and the so-called JTAG chain integrity refers to the JTAG Connector, FPGA, prom TMS, TCK, to ensure that the JTAG Connector TDI is formed between its tdo and the tdi→ (TDI ~tdo) → (tdi~tdo) →jtag connector TDO "closed loop, where (TDI~TDO) is a pair of input and output pins of the FPGA or prom chip itself. The JTAG chain of the configuration circuit in Figure 5-12 is from the TDI of the connector to the TDI of the FPGA, from the tdo of the FPGA to the TDI of the prom, and finally from the tdo of the prom to the tdo of the connector, forming a complete JTAG chain, which is called the first chip of the chain. You can also change the location of the FPGA and prom as needed so that the prom becomes the first chip in the chain.

(2) Power supply compatibility

5-22, as the FPGA and prom to complete data communication, the interface level must be consistent, that is, the FPGA corresponding packet pin voltage vcco_2 must be the same as the prom Vcco input voltage, and the ideal value of 2.5V, which is due to the FPGA Prog_ B and done pins are powered by the vccaux of 2.5V. In addition, because the voltage of the JTAG connector is also provided by the Vccaux of 2.5V, the VCCJ of the prom must also be 2.5V. Therefore, if the interface voltage is different from the reference voltage, the pin voltage and the reference voltage of the corresponding packet must be set to the same at the configuration stage, and then switched to the operating voltage required by the user when the configuration is complete. Of course, the FPGA and prom can also adapt to the 3.3V I/O level as well as the JTAG level, but some changes need to be made to add several external current limiting resistors, as shown in 5-22. In the main string mode, the nuclear pressure of the XCFXXS series Prom must be 1.8V for the 3.3V,XCFXXP series prom.

Figure 5-22 3.3V JTAG configuration circuit

Figure 5-22 Rser, rpar these two resistors to pay special attention. First, the rser= 68ω limits the current flow into each input to 9.5mA, followed by a 33-input diode conduction,

Rpar = Vccaux Min/niin = 2.375v/(3*9.5ma)
=83ω or 82ω (resistors with standard value error less than 5%)

(3) Signal integrity of the CCLK

CCLK signal is the clock signal of JTAG configuration data transmission, its signal integrity is very critical. The FPGA configuration circuit has just begun to work with the lowest clock, and if not specifically specified, will gradually increase the frequency. The CCLK signal is generated internally by the FPGA, and the maximum value for different chips and levels is shown in table F-1.

Table 5-1 maximum configuration clock frequency for different prom chips

3. Configuring multi-Chip FPGAs

The configuration circuit of the multi-chip FPGA is similar to that of the monolithic one, but there are Master (master) and Slave (Slave) between the multiple pieces of FPGA, and different configuration modes need to be selected. Two pieces of Spartan 3E series FPGA typical configuration circuit 5-23, two pieces of FPGA has the main, from the status of the points.

Figure 5-23 Configuration circuit for two-piece FPGA in master-slave mode

5.5.3 SPI serial Flash configuration mode

1. Introduction to SPI serial configuration

Serial Flash is characterized by a small footprint, as the system of data storage is very appropriate, generally using a serial peripheral interface (SPI bus interface). Flash memory and EEPROM are fundamentally different characteristics of the EEPROM can be written in bytes of data rewriting, and flash can only erase an interval, and then rewrite its content. In general, this erase interval is called sector (Sector), and some manufacturers introduce the concept of page. When selecting a flash product, the minimum erase interval is a more important indicator. When writing to Flash, if the data is not exactly the size of a minimum erase interval, it is necessary to save the entire interval of data to the other storage space, erase the space, and then re-rewrite the interval. Most flash processes make it easier to achieve larger erase intervals, so flash for smaller erase intervals is typically slightly more expensive. In addition, the SPI is a standard 4-wire synchronous serial bidirectional bus that provides serial communication data links between the controller and peripherals and is widely used in embedded devices.

Xilinx's new FPGAs support the SPI interface. SPI bus through 4 signal lines to complete the main, from the communication between, typical SPI system often contains a master device and at least one slave device, in the FPGA application, FPGA chip-based device, SPI serial flash for the slave device. The names and functions of the 4 SPI interface signals are shown in table 5-2.

Table 5-2 SPI interface Signal List

A master chip and a communication interface from the chip are shown in 5-24. FPGA through the SCLK control the timing of the communication between the two sides, when the ss_n is low, the FPGA through the MOSI signal line to transmit data to flash, in the same clock cycle, flash through the Somi data transmission to the FPGA chip. Regardless of the master, slave device, the data is output at the clock level jump, and at the next opposite level jumps along, feeds another chip.

Figure 5-24 SPI Interface Connection

wherein the SCLK signal supports different rates, generally used 20MHz. The two bits of Cpol and Cpha in the SPI interface define 4 communication timings. wherein, the CPOL signal defines the idle state of the SCLK, when the Cpol is low, the low level of SCLK is idle, otherwise its idle state is high, CPHA defines the valid rising edge position of the data, when it is low, the data is valid at the 1th level jump edge, otherwise the data is valid at the 2nd level jump edge. The corresponding timing logic 5-25 is shown.

Figure 5-27 Bus timing for low-time SPI Cpha

Figure 5-28 Bus timing for high-time SPI Cpha

It is possible to support multiple slave devices by increasing the bit width of the chip selection signal Ss_n, and the ss_n bit width equals the number of devices. The read-write timing logic is the same as for a selected slave and master device at some point, as in Figure 5-29.

Figure 5-29 Connection circuit diagram for multiple slave chips

As a new high-performance nonvolatile memory, SPI serial flash can read and write as many as millions of times, not only the number of pins, small package, large capacity, save board space, but also reduce power consumption and noise. Functionally, it can be used for code storage as well as for large volumes of data and voice storage, and serial storage that supports partitioned (multi-page) Erasure and Page writes is the best solution for applications that are read-only and have only a small amount of write-write time.

2. SPI serial Flash configuration circuit

The SPI serial configuration mode is often used in systems that have an SPI serial flash prom, where configuration data is loaded into the FPGA at power-up, and the process simply sends a 4-byte instruction to the SPI serially, and the data in the serial flash is continuously loaded into the FPGA as if it were a prom configuration. Once configured, additional storage space in the SPI can also be used for other application purposes.

1) SPI configuration circuit

Although the SPI interface is a standard 4-wire interface, different SPI FLASH prom chips use different instruction protocols. The FPGA chip uses variable selection signal vs[2:0] to define the way in which the FPGA and SPI Flash are communicated, the read instruction of the FPGA, and the number of redundant bits inserted before the data is effectively received. Common SPI Flash and FPGA effective operation configuration as shown in table 5-3, the rest of the vs[2:0] configuration is reserved for its use.

Table 5-3 the SPI flash memory supported by the Turing chip and the configuration list

As a whole, it is easier to control the SPI serial flash, which requires only simple instructions to read, erase, program, write enable/disable, and other functions. All instructions are entered via a serial shift of 4 SPI pins.

Figure 5-30 Serial Flash configuration circuit that supports fast read and write

Different types of FPGA chips have a number of different slave device chip selection signals, so the number of serial chips hanging is not the same. For example: SPARTAN-3E series FPGA chip only 1-bit SPI from the device chip selection signal, so only a piece of SPI serial flash chip. In SPI serial flash configuration mode, m[2:0]=3 ' b001. After the FPGA is powered up, the configuration is done via an external SPI serial flash prom, and the clock signal is provided by the FPGA chip to provide clock signals, supporting two types of industry-commonly used flash.

Figure 5-30 shows a typical configuration circuit for the Stmicro 25 series prom with the SPARTAN3E series FPGA support for 0x0b Fast read-write instructions. The flash chip requires the Flash programmer to load the configuration data, and the monolithic FPGA chip forms the complete JTAG chain, which is used only to test the chip status and to support the JTAG inline debug mode, which is not related to the SPI configuration mode.

It can be seen that the SPI flash capacity is large, suitable for large-scale design occasions. However, due to the SPI configuration requires a dedicated flash programmer, and the operation is cumbersome, not suitable for the development phase of the FPGA chip debugging, it is generally also added JTAG chain dedicated to online debugging.

Figure 5-31 Atmel SPI serial Flash configuration circuit

Figure 5-31 shows a typical configuration circuit for the Atmel Company "C", "D" series of serial flash chips that support the SPI protocol in the SPARTAN3E series FPGAs. These two series of flash chips can work at very low temperatures and have a short clock settling time. Similarly, monolithic FPGA chips make up the complete JTAG chain, are used only to test the chip status, and support the JTAG inline debug mode, which is not related to the SPI configuration mode.

Table 5-3 shows the connection of the SPI configuration interface, the name of each SPI Flash prom is slightly different, the SPI Flash Prom write protection signal and hold control signal in the FPGA configuration phase is not used. wherein the hold PIN must be high in the configuration phase, in order to program flash memory, the write protection signal must be high.

5.5.4 from String configuration mode

In serial mode, an external host such as a microprocessor or microcontroller is required to write the configuration data serially to the FPGA chip via a synchronous serial interface, whose mode selection signal m[2:0]=3 ' b111. Typical Spartan 3E series FPGA single-chip configuration circuit 5.5.11 is shown. The serial configuration data for the DIN input pins requires sufficient settling time before the external clock cclk the signal. One monolithic FPGA chip makes up a complete JTAG chain, is used only to test the chip status, and supports JTAG inline debug mode, which is not related to the string configuration mode. The external host starts the configuration with the drop-down Prog_b and detects the init_b level, and when the init_b is high, it indicates that the FPGA is ready to begin receiving data. At this point, the host begins to provide data and clock signals until the FPGA is configured and the done pin is high, or the init_b is lowered to indicate that a configuration error has occurred. The entire process requires more clock cycles than the profile size, which is due to the partial clock used for timing setup, especially when the FPGA is configured to wait for the DCM to latch its clock input.

Figure 5-32 FPGA from the string configuration circuit

In addition, multi-chip FPGA chips can also be configured from the string configuration mode, typical of the two Spartan 3E series FPGAs from the string configuration circuit 5-33 shown. All chip CCLK signals are provided by a master device, and the FPGA near the master device acts as a bridge to forward the configuration data to a second FPGA chip. It can be seen that the benefits of adopting a string configuration are mainly to save the board area and make the system more flexible.

Figure 5-33 Multi-chip FPGA configuration circuit from the string mode

5.5.5 JTAG Configuration mode

1. JTAG Configuration Circuit

Xilinx's FPGA chip has the JTAG interface specified by the IEEE 1149.1/1532 protocol, which can be used as long as the FPGA is power-up, regardless of the mode selection pin m[2:0] level. However, when the mode configuration pin is set to JTAG mode, i.e. M[2:0]=3 ' b101, the FPGA chip can only be configured via JTAG mode after power-on or a low pulse of the Prog_b pin appears. The JTAG mode does not require additional power-down nonvolatile memory, so the bit files configured by them are lost after the FPGA is powered down and need to be reconfigured each time it is power-up. Because the JTAG mode has been changed, the configuration efficiency is high, which is an essential configuration mode in the project development phase. The typical Spartan 3E series chip is shown in JTAG configuration circuit 5-34.

Figure 5-34 JTAG Mode configuration circuit

5.5.6 System ACE Configuration Scenario

As FPGAs become at the heart of system-level solutions, large, complex devices often require multiple, large-scale FPGAs. If you use a prom for configuration, it requires a large PCB area and high cost, so in many cases the use of micro-processing from the FPGA chip configuration, but the configuration scheme is prone to bus competition and extended system boot time. In order to solve the problem of large-scale FPGA configuration, Xilinx has introduced system-level systems ACE (Advanced Configuration Environment) solutions.

System Aces can be configured on all Xilinx FPGAs in one system, or even on multiple boards, using flash memory cards or micro drives to save configuration data, and configure the data in the FPGA with the system ACE Controller. Currently, System Ace has system ace
Three kinds of CF (Compact Flash), System Ace SC (Soft Controller) and System Ace MPM (Muti-package Module). The reader should note that system Ace SC/MPM is a standalone solution with System Ace CF. The typical ACE interface and system composition are shown in 5-35.

Figure 5-35 Typical ACE interface and system composition

1. System ACE CF Solution

The core of System Ace CF is the system Ace CF storage device and the system ACE Controller chip. System Ace CF storage devices include Xilinx's ace Flash card or other manufacturer's compact Flash card and IBM's Micro drive. Compact Flash card capacity is 32MB~4GB, the capacity of the micro-drive is 2GB~6GB, at least hundreds of chip FPGA chip can be configured.

The System ACE CF Controller provides the interface between the storage unit and the FPGA device, and the standard JTAG interface for PC and memory. The default configuration mode of the controller chip is also to configure the data in the FPGA chain by the boundary scan method, and the test and programming interface of the boundary scan chain can be used to assist the system prototype debugging, and its main features are:

-Support the configuration of all Xilinx FPGA chips;
-Up to 8Gb configuration with minimal PC board space;
-Includes up to 152Mbps configuration rate;
-System adjustment using FPGA with embedded processor core;
-Manage multiple bit streams (all or part) and activate them as needed;
-Contains processor core initialization;
-Software storage encryption;
-Removable memory parts;
-Reduces the cost of custom configuration systems, supports most CompactFlash cards, including microdrive units, includes built-in microprocessor interface, can directly adjust FPGA configuration, release design resources.

Figure 5-36 System ACE CF configuration circuit

The Compact Flash interface is the key interface for the ACE Controller, which connects the Compact Flash card, the standard Compact Flash module, and the IBM Micro Drive. Compact Flash can be disassembled, making it easy to modify and upgrade storage content and replace capacity. The Compact Flash interface consists of the compact Flash controller and the compact Flash arbiter. The interface circuit 5-36 of the FPGA configured by System ACE CF is shown.

2. System ACE SC Solution

System ACE SC provides the user with the freedom to choose each part of the component, which can be placed anywhere on the board, and all functions are done in a separate FPGA without the need to integrate other components. The System ACE SC has 4 main interfaces: Boundary-Scan JTAG Interface, System control interface, flash memory interface, and FPGA interface, as shown in 5-37.

Figure 5-37 System ACE SC interface

The JTAG interface mainly provides the boundary scan test and the flash memory communication with the JTAG interface, the Flash interface mainly communicates with the outside Flash chip, reads the contents of the memory and programs the memory, and the system control interface mainly provides the input clock, Configuration of control signals and configuration status signals, etc. the FPGA interface is primarily used to configure the FPGA, which can be configured from the serial, Slave, and Selec tmap modes.

The main difference between system Ace SC and system Ace CF is that the controller of the system Ace SC is a soft core logic, not a chip, which needs to be downloaded to FPFA together with the design. The remaining differences are listed in table 5-4.

Table 5-4 system Ace CF and system ace SC differences

Typical system ACE SC configuration circuit 5-38 is shown.

Figure 5-38 System ACE SC configuration circuit

3. System ACE MPM Solutions

System ACE MPM is an integrated component solution that includes a configuration control component consisting of an FPGA and a prom and a flash storage component, packaged as a module to implement the configuration circuit with as few components as possible. Xilinx has 16M, 32M, and 64M bit low density system ACE MPM. System Ace MPM has 4 primary interfaces, like the system Ace SC interface, with the same features and functionality as the System Ace SC. The difference between the two is that the system ace MPM encapsulates the entire configuration module, while the system Ace SC allows the user to configure itself, as shown in the interface circuit 5-39.

Figure 5-39 System ACE MPM interface Circuit

System ACE MPM is Xilinx's first configuration to support bit-stream compression, supporting multiple configuration modes, as well as up to 8 FPGA chains from the serial configuration mode and up to 4 FPGA select map configuration modes with a maximum configuration rate of 152Mbps. At the same time, the board space and wiring can be minimized. Typical system ACE MPM configuration circuit 5-40 is shown. In summary, System ACE Technology simplifies the configuration of large FPGA systems, enabling developers to focus primarily on improving system performance and shortening development time.

Figure 5-40 System ACE MPM configuration circuit

FPGA development--configuration circuit

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