FPGA floating point unit design

The storage format of floating point in memory is as follows:

Address + 0 + 1 + 2 + 3 content seee eeee emmm mmmm here s represents the symbol bit, 1 is negative, 0 is the power of positive e offset 127, binary level code = (eeeeeeee)-127. The M 24-bit ending number is stored in 23 bits, only 23 bits are stored, and the highest bit is fixed as 1. This method uses the smallest number of digits to achieve a higher number of valid digits, improving the accuracy. Zero is a specific value, and the power is 0 or 0. The floating point-12.5 is stored in the storage area as a hexadecimal number 0xc1480000. The value is as follows: the conversion between address + 0 + 1 + 2 + 3 content 0xc1 0x48 0x00 0x00 floating point number and hexadecimal equivalent save value is quite simple. The following example shows how to convert the value-12.5. The floating point storage value is not a direct format. to convert it to a floating point number, the bits must be separated as listed in the above floating point storage format table. For example: address + 0 + 1 + 2 + 3 Format seee eeee emmm mmmm binary 11000001 01001000 00000000 00000000 hexadecimal C1 48 00 00 from this example we can get the following information: the sign bit is 1, indicating that a negative power is binary 10000010 or decimal 130,130 minus 127 is 3, which is the actual power. The ending number is the subsequent binary number. 10010000000000000000000 there is an omitted decimal point and 1 on the left of the ending number. This 1 is often omitted in the preservation of the floating point number, plus a 1 and the beginning of the decimal point to the ending number, the final value is as follows: 1.10010000000000000000000. Then, adjust the ending number according to the index. A negative index moves the decimal point to the left. A positive index moves the decimal point to the right. because the index is 3, the tail number is adjusted as follows: 1100.10000000000000000000 is a binary floating point number, and the binary number on the left of the decimal point represents the power of 2, for example, 1100 represents (1*2 ^ 3) + (1*2 ^ 2) + (0*2 ^ 1) + (0*2 ^ 0) = 12. The right of the decimal point also represents the power of 2, but the power is negative. Example :. 100... represents (1*2 ^ (-1) + (0*2 ^ (-2) + (0*2 ^ (-2 ))... = 0.5. The sum of these values is 12.5. Because the set symbol bit indicates that the number is negative, the hexadecimal value 0xc1480000 indicates-12.5.

The floating point units in FPGA pipeline form are as follows:

Step 1: Check whether it is in the abnormal area (the index is zero). If it is in the normal area, add the highest bits from logic 1 to the ending number (that is, change the ending number to 24). Otherwise, add zero. Based on this principle, the larger the data size, the lower the decimal point precision.

Step 2: the smaller values of the two numbers must be adjusted to make the index of the ending number equal. because the number of decimal places accounts for a small number, the ending number of the decimal places must be removed so that the data is exponentially aligned, that is, normalization. You can shift the difference between the two indexes to the right.

Step 3: Check the symbols and perform addition and subtraction, and then perform normalization.

It can be seen that the hardware implementation of addition and subtraction of floating point numbers is very complicated, so it is more complicated to implement the hardware multiplier.