FPGA DDR3 Debugging

FPGA DDR3 Debugging

SPARTAN6 FPGA chip integrates the MCB hard core, it can support to DDR3. The MiG IP core is available in Xilinx's development tools Xilinx ise, which designers can use to directly generate the DDR3 controller design module and complete the configuration via the MIG GUI graphical interface.

First, establish the ISE project and add the MiG IP core,

Next to the MiG IP core configuration, the main sections are listed here,

Here choose the type of DDR and choose which bank to use SPARTAN6, and select the bank on the left,

Here you set the clock frequency of the DDR3 and the DDR3 device model, Xilinx lists some of the DDR3 models, and if not, you need to click "Create custom Part" to customize the model, Note here that when customizing the model, it is best to choose a template that is the same as your DDR3 model data bit width, because the data bit width cannot be modified in the custom options (you can also modify the bit width in the generated code), and in the custom interface, the main settings are several time parameters related to DDR3 and the address line width. This information can be found on the chip's datasheet,

Here choose a different port mode, you can select a port, you can choose a different bit width of multiple ports, select multiple ports, you can read and write control of different ports, which is useful in ping-pong mode operation DDR3 (such as the use of P0 port to address 1 write operations, while using the P1 port to address 2 read operation ; When a read-write is completed, the P0 Port writes to address 2 while using the P1 port to read the address 1, and the address mapping relationship can be viewed: Spartan-6 FPGA Memory Interface Solutions and Spartan-6 FPGA Memory Controller),

The pins for RZQ and Zio are set up here, depending on the hardware circuit to choose, and you can choose whether to use Chipscope debugging, if you add chipscope you do not need.

After generating the MiG IP core, you can create a new project, copy the following files under the User_design file (select Add yourself), and then make the code modifications.

First of all, the modification of the constraint file, so that it is consistent with its own hardware devices, generally have the following points:

1, Vccaux voltage modification

CONFIG vccaux=3.3; # Valid values are 2.5 and 3.3

2, the system clock input cycle, need to be the same as the crystal frequency on the PCB board.

NET "MEMC3_INFRASTRUCTURE_INST/SYS_CLK_IBUFG" tnm_net = "SYS_CLK3";

Timespec "Ts_sys_clk3" = PERIOD "SYS_CLK3" NS high 50;

3, modify some pin voltage and position, such as clock, reset pin, etc.

Next, complete the settings for the top-level file, usually with the following points:

1. The reset polarity is consistent with the PCB board

2, according to the clock on the board to modify the DDR3 clock configuration section, I use a clock input of 50Mhz, because the DDR3 set in MiG frequency of 312.5MHz, and DDR3 is the upper and lower sampling, so the FPGA internal DDR3 controller clock needs 625MHz, So here first the clock frequency multiplier 25, then divide 2, get 625Mh CLKOUT0 and CLKOUT1, and then divide 8 respectively get the user interface clock and calibration clock 78.125Mhz.

3. Delete Mcb_traffic_gen related code, write your own DDR3 test code, and instantiate

4, write DDR3 test code, you need to refer to Spartan-6 FPGA Memory controller in the read and write timing, the main reference, mainly including commands, data, address, this test, because the use of 128bit single port, so each write a data, address line needs to add 8, If it involves burst reading and writing, the address line should also be increased by a multiple of 8.

5, finally add Chipscope, complete the test

FPGA DDR3 Debugging