FPGA implementation of histogram statistics

Histogram statistics is one of the most basic and common algorithms in image processing algorithm, the main principle is to calculate and count the number of pixels in each gray level in the image, which is more common in some algorithms for statistic of gray-scale characteristics. Although the histogram statistics in MATLAB or software is time-consuming, but now with the popularity of FPGA, more rapid implementation of some image processing algorithms become mainstream.
FPGA implementation of image processing algorithm now has several mainstream ways: 1, HDL Pure logic code, 2, based on the system generator module construction, 3, Xilinx company Vivado Suite in the HLS software for C + + code conversion.
This paper mainly adopts the first method, that is, the histogram statistic algorithm is realized directly by using Verilog code form.

• Method 1: Multiply frequency operation
• Method 2: Adjacent data judgment

Frequency multiplier operation

The first response to the histogram statistic is to set up 256 registers according to the method in the software, then make a judgment on each pixel size and then do +1 for the corresponding register, and in FPGA can take full advantage of the internal RAM to complete this operation. And here we are using pseudo-dual-port RAM.
In pseudo-dual-port RAM, it is important to have two setup options:

1. Primitives Output Register
This setting is mainly to add a register to the output port of RAM, and to make a beat cache operation on the output data. If this is checked, in the case of high frequency clock, the output signal can be effectively guaranteed to meet the setup and hold time. While the RAM itself reads the data delay to a beat, the total delay of the RAM readout data is 2 clock units.
2, Operating Mode
Mainly includes the no change, Write first and read first, as the name implies, mainly refers to the order of reading data. In the no change mode, the write operation does not alter the output data, in the write first mode, if the same address read and write, then read, in the read-first mode, if the same address reads and writes, read and write.

The code for the octave mode is as follows: (The Primitives Output Register is not checked in this routine and operating mode is set to write first)

Module His_count (Input Rst_n,input clk_150m,150Minput Lval,The companion enable signal for data input [7:0]dataInput 2K image, continuous data stream); reg LVAL_TEMP1,LVAL_TEMP2; reg [7:0]data_temp1,data_temp2;reg [20:0]addra; reg [7:0]dina;reg Ena,wea;reg [20:0]addrb;reg Enb;reg [8:0]count=9 ' D0;wire [7:0]doutb;wire clk_300m;clk_wiz_1 Clk_pll_inst (Clock in Ports clk_in1 (clk_150m),150M. CLK_OUT1 (clk_300m),300M. Reset (),Input reset. Locked ());Output lockedThe read-out delay of RAM is set to 1blk_mem_gen_1 L1 (. Clka (clk_300m),. Ena (ENA),. WEA (WEA),. Addra (Addra),. Dina (Dina),. Clkb (clk_300m),. Rstb (),. ENB (ENB),. ADDRB (ADDRB),. DOUTB (DOUTB)); Always @ (Posedge clk_150mor Negedge Rst_n)Beginif (!rst_n)Begin {Lval_temp2,lval_temp1}<=2 ' D0; {data_temp2,data_temp1}<=+ ' D0;EndElseBegin {lval_temp2,lval_temp1}<={lval_temp1,lval}; {data_temp2,data_temp1}<={data_temp1,data};EndEndRead module always @ (Posedge clk_150mor Negedge Rst_n)Beginif (!rst_n)Begin enb<=0; addrb<="D0;EndElsebegin enb<=lval; addrb<={' D0,data}; End End //write module always @ (Posedge clk_300m or Negedge rst_n) begin if (!rst_n) begin ena<=0 ; wea<=0; addra<=' D0; dina<=8 ' D0; end Else begin ena<=lval_temp2; wea<=lval_temp2; addra<={' d0,data_temp2}; dina<= doutb+1; End End                  

Adjacent number judgment

The number of neighbors is judged primarily by determining whether the previous pixel is the same as it is to change the data written by RAM. Since there is at least one delay in the readout of RAM, if the number of neighbors encounters the same situation, the value written by the previous number cannot be read by the latter number, so it will encounter the case of a drain count. If the number of neighbors to judge the way, you can avoid the frequency multiplier caused by the timing problem.
In this case, Operating mode is set to write first. And the Primitives Output Register is not checked.
The code is as follows:

Module His_count (Input Rst_n,input clk_150m,150Minput Lval,The companion enable signal for data input [7:0]dataInput 2K image, continuous data stream); reg LVAL_TEMP2,LVAL_TEMP1; reg [7:0]data_temp2,data_temp1;reg [20:0]addra; reg [7:0]dina;reg Ena,wea;reg [20:0]addrb;reg Enb;wire [7:0]DOUTB;The read-out delay of RAM is set to 1blk_mem_gen_1 L1 (. Clka (clk_150m),. Ena (ENA),. WEA (WEA),. Addra (Addra),. Dina (Dina),. Clkb (clk_150m),. Rstb (),. ENB (ENB),. ADDRB (ADDRB),. DOUTB (DOUTB)); Always @ (Posedge clk_150mor Negedge Rst_n)Beginif (!rst_n)Begin {Lval_temp2,lval_temp1}<=2 ' D0; {data_temp2,data_temp1}<=+ ' D0;EndElseBegin {lval_temp2,lval_temp1}<={lval_temp1,lval}; {data_temp2,data_temp1}<={data_temp1,data};EndEndRead module always @ (Posedge clk_150mor Negedge Rst_n)Beginif (!rst_n)Begin enb<=0; addrb<="D0;EndElseBegin enb<=lval; addrb<={' D0,data};EndEndWrite module always @ (Posedge clk_150mor Negedge Rst_n)begin if (!rst_n) begin ena<=< Span class= "Hljs-number" >0; Wea<=0; Addra<=21 ' D0; dina<= 8 ' D0; end else if (data_temp2 = = Data_ TEMP1) begin ena<=lval_temp2; wea<=lval_temp2; addra<={ 14 ' D0,DATA_TEMP2}; Dina<=doutb+2; end else begin ena<=LVAL_ Temp2; wea<=lval_temp2; Addra<={14 ' d0,data_temp2}; dina<=doutb+1; end end          

FPGA implementation of histogram statistics