FPGA implementation of SRAM

the SRAM read and write simulation did not carry out the SRAM ping-pong operation, just a single SRAM read and write operations, SRAM read and write operations do not need to refresh operation, write the port includes: Write clock, write address, write data, write enable; Read port includes: Read clock, read address, Read data, read enable.
Among them, write enable and read enable signal control is more important, only in read enable or write to enable the effective, read operation or write operation is effective, so in the SRAM read and write logic, should pay attention to write to write address, write data coordination between read enable and read address, read the data between the coordination.
In the case of the write enable signal is invalid, it should stop the write address of the self-increment and data write operation, because the write invalid, the data will be automatically discarded, the next write can be effective, can not determine the start address of the write address, so that the processing of data confusion, in the case of read enable signal, should stop the read address of the Because the read enable is invalid, the read address self-increment will not have the data output, the next time a read enable to be valid, cannot determine the current read address, also can make the data chaotic.
Here, I am doing the experiment, first write operation, write full, after the read operation. Write address from small to large, write data increment, for example, address bit width is 5 bit, that address space is 5 ' b0 to 5 ' b11111, where the data bit width is set when referring to the IP core, depth is also in the reference IP core when set. The readout data is transmitted to the serial TX module via FIFO, with a baud rate of 9600 (main clock 25MHz).

Debugging process encountered in the problem is, because the speed of the serial port and SRAM read and write rate is too different, in the SRAM write FIFO, after the FIFO full, SRAM does not stop reading and writing operations, that is, SRAM read and write operations and FIFO write operation is almost independent, which leads to The data written FIFO is not sequential but chaotic, in the debugging process, found that there is data output, but the data order is not correct, presumably read and write should not be a problem, the main problem should be read and write control signal uncoordinated, after improved, the data can be printed as intended, I was so improved, Only one write SRAM operation, write full after only one read operation, so that the SRAM has been read and write caused by the data is overwritten by the problem of data chaos.

Let's take a look at the experimental process:
The first is the RTL diagram for the entire experiment:

SRAM Configuration page:

SRAM read-Write timing simulation diagram:

We can see that when write enable is high (enable signal high), read enable is low, and when read enable is high, write enable is low level.
When write is enabled, both the write address and the write data are incremented, and when they are valid, the read address changes accordingly, and the write address and the write data stop changing.
The relationship between the specific geological changes and the enabling signals is shown in the following: (note: The Write address and write data are incremented in the experiment, the read address is decremented at the highest address, so we see the print data should be decremented)
Is the sequence diagram that writes the enable signal, writes the data, writes the Enable signal:

We find that when write enable is high, the read enable is low, the read address remains the same, and the write address starts from 0 addresses and the data starts to change.
The following is the read timing of the SRAM:

The following is the control module source code (need a complete code can leave a message):

Module Sram_control (clk,sys_rst,wr_en,wr_data,wr_address,rd_en,rd_address,fifo_wr_req,wrfull); input Clk;inputsys _rst;inputwrfull;output wr_en;output [7:0] wr_data;output [4:0] Wr_address;output rd_en;output [4:0] Rd_address;o Utputfifo_wr_req;reg [7:0]wr_data_r;reg [4:0]wr_address_r;reg wr_en_r;reg wr_en_r1;reg [4:0]rd_address_r;reg [4:0]rd] _address_r1;reg rd_en_r;regrd_en_r1;regrd_en_r2;//Write the address of the SRAM [email protected] (Posedge CLK or Negedge sys_rst) if ( !sys_rst) Wr_address_r <= 5 ' D0;else if ((Wr_address_r < 5 ' b11111) && (wr_en_r)) Wr_address_r <= wr_ Address_r + 1 ' b1;else if (rd_address_r = = 5 ' D1) wr_address_r <= 5 ' d0;else wr_address_r <= wr_address_r;//write SRAM data [EMA Il protected] (Posedge CLK or Negedge sys_rst) if (!sys_rst) wr_data_r <= 8 ' D0;else if ((Wr_data_r < 8 ' b1111_1111 ) && (Wr_address_r < 5 ' b11111)) Wr_data_r <= wr_data_r + 1 ' b1;else if (wr_data_r = = 8 ' b1111_1111) Wr_data_r &lt = 8 ' d0;else;//write Enable [email protected] (Posedge CLK or Negedge sys_RST) if (!sys_rst) Wr_en_r <= 1 ' b1;//else if (Wr_address_r < 5 ' b11110) wr_en_r <= 1 ' b1;else if (wr_address_r! = 5 ' b 11111) Wr_en_r <= 1 ' b1;else wr_en_r <= 1 ' b0;//read SRAM address//Address reverse read out [email protected] (Posedge CLK or Negedge Sys_rst if (!sys_rst) Rd_address_r <= 5 ' b11111;else if (!wr_en_r) rd_address_r <= rd_address_r-1 ' b1;else if (Rd_address_r = = 5 ' D0) rd_address_r <= 5 ' b11111;else rd_address_r <= 5 ' b11111; [Email protected] (Posedge CLK or Negedge sys_rst) if (!sys_rst) rd_address_r1 <= 5 ' d0;else rd_address_r1 <= rd_address_r;//read enable [email& Nbsp;protected] (Posedge CLK or Negedge sys_rst) if (!sys_rst) Rd_en_r <= 1 ' b0;else if (wr_address_r = = 5 ' b11111) rd_en_r <= 1 ' b1;else rd_en_r <= 1 ' b0; [Email protected] (Posedge CLK or Negedge sys_rst) if (!sys_rst) beginrd_en_r1 <= 1 ' b0;rd_en_r2 <= 1 ' b0;endelse beginrd_en_r1 <= rd_e N_R;RD_EN_R2 <= rd_en_r1;endassign wr_en = Wr_en_r;assignwr_data = Wr_data_r;assignwr_address = Wr_address_r;assign Rd_en= Rd_en_r;assignrd_address = Rd_address_r;assignfifo_wr_req = ((!wrfull) &&rd_en_r2)? 1 ' b1:1 ' B0;endmodule 

FPGA implementation of SRAM