FPGA key to shake Verilog code

The reason for the key to shake and its classification will not be wordy.

Here to explain a piece of code, code is online search, looked at half a day did not understand, helpless to find a half-day to think for a long time, finally understand ...

Module Sw_debounce (
Class
Rst_n,
SW1,
SW2,
SW3,
Output
LED_D3,
LED_D4,
Led_d5
);
Input CLK;
Input rst_n;
Input SW1,SW2,SW3; Active Low
Output led_d3;
Output led_d4;
Output led_d5;
// ---------------------------------------------------------------------------
The input of SW1~SW3 is filtered by low-pass filter, and the high frequency component is filtered to get LOW_SW value.
// ---------------------------------------------------------------------------
reg [19:0] CNT;
Always @ (Posedge CLK or Negedge rst_n)
if (!rst_n)
CNT <= ' D0;
Else
CNT <= CNT + 1 ' B1;
reg [2:0] LOW_SW;
Always @ (Posedge CLK or Negedge rst_n)
if (!rst_n)
LOW_SW <= 3 ' b111;
else if (cnt = = HFFFFF)//Every 20MS check button
LOW_SW <= {SW3,SW2,SW1};
// ---------------------------------------------------------------------------
// ---------------------------------------------------------------------------
reg [2:0] low_sw_r; Locks the LOW_SW signal to a clock cycle, and the delay is not a true "latch"
Always @ (Posedge CLK or Negedge rst_n)
if (!rst_n)
Low_sw_r <= 3 ' b111;
Else
Low_sw_r <= low_sw;
Wire [2:0] Led_ctrl = low_sw_r[2:0] & (~low_sw[2:0]);
The key is pressed when the key is detected to have a falling edge, the button is valid
Reg D1;
Reg D2;
Reg D3;
Always @ (Posedge CLK or Negedge rst_n)
if (!rst_n)
Begin
D1 <= 1 ' B0;
D2 <= 1 ' B0;
D3 <= 1 ' B0;
End
Else
Begin
if (led_ctrl[0]) d1 <= ~d1;
if (led_ctrl[1]) D2 <= ~d2;
if (led_ctrl[2]) D3 <= ~d3;
End
Assign led_d5 = D1? 1 ' b1:1 ' B0;
Assign led_d3 = D2? 1 ' b1:1 ' B0;
Assign LED_D4 = d3? 1 ' b1:1 ' B0;
Specific principle: In general, the key jitter will produce 10--20ms Burr, so to do is actually in 20MS sampling once, when
When the key falling edge is detected, it is determined that the other state is ignored. With 50MHz crystal oscillator, the clock period is 20ns,
else if (cnt = = HFFFFF)//Every 20MS check button
LOW_SW <= {SW3,SW2,SW1};
reg [2:0] low_sw_r; Locks the LOW_SW signal to a clock cycle, and the delay is not a true "latch"
Always @ (Posedge CLK or Negedge rst_n)
if (!rst_n)
Low_sw_r <= 3 ' b111;
Else
Low_sw_r <= low_sw;
Wire [2:0] Led_ctrl = low_sw_r[2:0] & (~low_sw[2:0]);
The key is pressed when the key is detected to have a falling edge, the button is valid
Personally think, lock a clock cycle, the application in the FPGA is too much, almost all the procedures to use, the role of nothing but
is to prevent competitive adventures, to delay a signal by one clock cycle (low_sw_r[2:0]), the original signal to take the reverse (~low_sw[2:0]), 2
Signal, you can detect a change in the falling edge, resulting in a pulse with a width of one clock cycle (20ns),
This pulse is used as a control signal to control other processes ...

It's all turned from a brother's blog, and here I explain what it is about a locked-down cycle. The present is implemented through a non-blocking statement, always block is parallel, execution, non-blocking statement assignment is to calculate the value of the expression to the right of all the equations, and then assign values, during the calculation, that is, before the end of the constant block, the left side of the equation to wait for the assignment of the variable remains the original value, so , the second-level latch low_sw_r is always the last value of LOW_SW, thus enabling the signal to be latched into a cycle.

Wire [2:0] Led_ctrl = low_sw_r[2:0] & (~low_sw[2:0]); This is a very classic falling edge detection statement. Because the non-blocking assignment statement, Low_sw_r is low_sw the value of the previous period, and the period of the LOW_SW to reverse the phase, and the button is pressed whether the test results, 0 is not pressed, 1 is pressed.

Reprinted from: http://www.cnblogs.com/lamapig/archive/2010/10/03/1841537.html

FPGA key to shake Verilog code