FPGA knowledge Comb (d) Large summary of reset system in FPGA

This article integrates the Wu Houai and Coyoo (Wang min) blog posts of two great gods. I also highly respected the books of these two great gods, the privilege of books to the basis of the foundation, we do not want to listen to me to buy Coyoo. I am still the same sentence, do the technology will be step by step. Gossip less, straight into the subject.

One, asynchronous reset

Look at this circuit first, which is an example of an asynchronous reset. Reset uses Reg's return end

　　　　　　　　　　　　　　

It's like this in code.

1 ModuleReset_test (2 CLK,3 Rst_n,4 I_data,5 O_data6                         );7                     8 inputCLK;9 inputRst_n;Ten inputI_data; One Output     RegO_data; A  -  always@ (PosedgeAlor Negedgerst_n) -     if(!rst_n) O_data <=1'D0; the     ElseO_data <=I_data; -      - Endmodule 

Two, synchronous reset

The first is to see the circuit first, this is the QuartusPrime51.1 integrated synchronous reset program after the RTL Viewer

　　　　　　　　　　　　　　

The code is as follows

1 ModuleReset_test (2 CLK,3 Rst_n,4 I_data,5 O_data6                         );7                     8 inputCLK;9 inputRst_n;Ten inputI_data; One Output     RegO_data; A  -  always@ (PosedgeCLK) -     if(!rst_n) O_data <=1'D0; the     ElseO_data <=I_data; -      - Endmodule 

Careful classmates have not found, a lot of blog post inside the circuit diagram, input side there is not a 2 Choose 1 multi-channel selector, but a with the door. That's why I'm just stating that my QuartusPrime15.1 is a total. Of course this is not the focus, the focus is synchronous reset than asynchronous reset more use of the device. The data also passes through one device more.

Contrast:

The advantages of asynchronous Reset: 1, saving the device, which is particularly important in ASIC. 2, the propagation delay of the data path is reduced. Increased system response frequency. 3, effective immediately, does not depend on whether the clock is coming.

The disadvantage of asynchronous reset: Because the reset signal timing is uncertain, reset release will allow the asynchronous reset system to appear metastable.

Advantages of Synchronous Reset: 1, reducing the appearance of metastable state. Attention is lowered, not completely eliminated. If the reset glitch or the trigger point is not in the setup and hold time of the clock rising edge, it will be all right, but if it is not the point of time, there will still be metastable. 2, facilitates timing analysis. Since the synchronous reset signal must be captured by the clock to be effective, it is easy to be analyzed by the timing analysis tool to its margin slack

The disadvantage of synchronous Reset: 1, more use of the device. 2, increase the data path strength transmission time

Saving the device and increasing the F is the ASIC's battleground, so at present the great gods also like to improve on it, called synchronous release of asynchronous reset

3, synchronous release of asynchronous reset first edition

　　　　　　　　　　　　　　　　

This method is a first shot of the reset signal, removing the reset burr while reset release can also be achieved with the clock synchronization. On the surface it can be said to be a perfect solution.

However, the problem came out, a dream June once in the interview a post was asked this asynchronous reset synchronous release problem, when I draw the circuit diagram, the interviewer immediately asked me: If the clock hangs, your system is not yet reset it? I was suddenly speechless. Then you have to say, you are right, this really did not take into account. Of course, I say this is not to blame who, if not these great gods on the blog to dedicate their technical information, we can not understand so much, only blame ourselves did not go into the drill. I also hope that readers will be able to delve into my blog flaws.

Thank you very much for your knowledge of the FPGA (III.) Introduction to VERILOGHDL grammar (2) Knowledge Summary This blog post points out that the phrase "blocking used in assign" is meant to tell you that assign is using "=" instead of " <= ". There is nothing wrong with this understanding, but the expression is not correct, according to Veriloghdl_2001_standard,assign is continuous assignments (continuous assignment statement) There is no blocking non-blocking points, Blocking non-blocking is only for procedural assignment (procedural assignment statements), so assign is, of course, "=" behind.

Well, with all that said, it's time to go back to the asynchronous release of this synchronous reset.

4, improved synchronous release of asynchronous reset

　　　　　　　　　　　　　　

　　　　　　This is the use of Coyoo space diagram and program, because the new version of the RTL viewer Q is not intuitive.

Program is

1 //' Default_nettype None2 3 ModuleReset_test (4 Clock,5 Reset_n,6 Data_a,7 Data_b,8 Out_a,9 Out_bTen                         ); One                      A inputClock,reset_n; - inputData_a,data_b; - OutputOut_a,out_b; the  - Regreg1, REG2; - RegReg3, REG4;  -  WireRst_n; +  - AssignOut_a =REG1, +Out_b =REG2, ARst_n =REG4; at  -  always@ (PosedgeClockor Negedgereset_n) -     if(!reset_n)begin  -Reg3 <=1'D0; -REG4 <=1'D0;  -             End  in     Else begin  -Reg3 <=1'D1; toREG4 <=reg3; +             End  -      the  always@ (PosedgeClockor Negedgerst_n) *     if(!rst_n)begin  $REG1 <=1'B0;Panax NotoginsengREG2 <=1'D0; -             End  the     Else begin  +REG1 <=data_a; AREG2 <=Data_b; the             End  +      - Endmodule 

Reg3,reg4. Asynchronous reset generates Rst_n, and due to the timeliness of the asynchronous reset, all Reg will be reset. After the Reset_n is released, VCC is transferred to the Rst_n system only after the clock arrives. So the synchronous release is realized.

1, if the clock is not, Reset_n Reset, the system is still reset

2, if the REG3,REG4 asynchronous reset is released, the metastable state occurs. A) reg3 Reset, REG4 Reset is complete. Clock came reg4 to undertake reg3 q (n-1) =0 is still the reset state. B) reg3 Reset is complete, REG4 reset. Clock came reg4 to undertake reg3 q (n-1) =0 is still the reset state. Either way, the end is back to normal.

5, asynchronous reset synchronous release PLL version

FPGA knowledge Comb (d) Large summary of reset system in FPGA