FPGA New Nios

[FPGA] The first Nios II system design based on Qsys (2013-12-12 21:50:08) reproduced

Tags: FPGA niosii qsys helloword quartusii

Category: Embedded

[FPGA] The first Nios II system design based on Qsys

I. BASIC INSTRUCTIONS

1. Software platform: Quartus II 13.0 (64-bit)

Nios II 13.0 software Build Tools for Eclipse

2. Hardware platform: Altera Cyclone II ep2c8q208c8n

Second, the design goals

Complete the implementation of the "Hello Word" on the FPGA platform, using the Qsys-based Nios II system design.

Third, the specific steps

1. Open Quartus II 13.0 (64-bit), create a new project, File--New project Wizard ..., ignore introduction, and click Next> to proceed to the next step. Set up engineering working directory, project name respectively. It is important to note that in the engineering work directory, please use English, do not include spaces, etc., or you may have problems when using the Nios II IDE later . set as shown in 1. Then proceed to the next step.

Figure 1 Setting the project working directory, project name

2, add the existing files, here we do not need to add files, directly click Next> to enter the next step. For device setup. We use the Cyclone II family of EP2C8Q208C8 chips and choose well after going directly to the next step. EDA tool Setup, because we do not perform simulation in the project, so do not set up, if you need to Modelsim simulation, in the simulation line, select tool Name For Modelsim-altera (this is selected based on the version of Modelsim installed), Format (s) is selected as Verilog HDL (this is also selected based on the hardware description language mastered). Click Next>, go to the Summary (summary) page, and click Finish to finish.

3, new block diagram/schematic File (block diagram/schematic document). Click File, New, select Block Diagram/schematic File in the design files, and click OK. Results are shown in 2 when finished.

Figure 2 new block diagram/schematic File

4, start the Qsys tool, hardware part of the design. Click Tools, Qsys, and enter the Qsys Setup interface, shown in 3. The system has already added the clock module by default, the name is Clk_0, here we check clk_0, right click, select Rename, change its name to CLK. The following add any module, we make similar name changes, change the name of the method is similar, is not repeated narrative.

5. Add the parts of the soft core processor module. In total we need to add the 4 modules Nios II Processor, on_chipmemory (RAM or ROM), JTAG UART, and System ID peripheral. First, familiarize yourself with the Qsys interface. To the left component library, is a system-provided component libraries, there are some common modules that make up the processor. The right side is the module that has been added to the system, that is, the Nios II soft core processor can be customized to meet the specific needs. We search for Nios II Processor in the component library and can be configured by double-clicking. The first thing to choose is the type of Nios II core. The core of the Nios II soft core is divided into three types, E-type, S-type and F-type.

Figure 3 Qsys Setup Interface

The e-core occupies the least amount of resources and functions the simplest and slowest. S-type core occupancy resources Secondly, the function and speed are higher than the former, the F-type core has the most functions, the fastest, the corresponding occupation resources are the most, choose the time according to demand and chip resources to decide, here we choose S core. Then click Finish to end the current configuration.

Add the on-chip memory below to search for the on chip memory in the component library. Double-click to set. We mainly set the data width and total memoy size in size. Data width is set to a bit width, where we set it to 16 bits. Total Memoy size is set on the on-chip resources and needs to be set appropriately based on the chip resources, where we set the 10240 bytes. Click Finish to end the current configuration.

Add the JTAG download Debug interface below. Search for the JTAG UART in the component library. Double-click to set. Since our system has no special requirements, we choose the default configuration here. Click Finish to end the current configuration.

Add the System ID module below. The system ID is the unique identifier of the system that distinguishes it from other systems. Search the component library for system ID peripheral, and double-click to set it up. Here we set it casually, as set to 1234. Click Finish to end the current configuration.

The following lines need to be done, will be the right connections column in the relevant line through the setting node to connect. First, all modules of CLK and reset reset need to be connected. Then the on-chip memory On-chip memory S1 and the processor Nios2_qsys Data_master and Instruction_master connected. The Jtag Debug Module Jtag_uart avalon_jtag_slave is connected to the data_master of the processor Nios2_qsys. The System ID module Sysid_qsys Control_slave is connected to the data_master of the processor Nios2_qsys. Finally, the processor Nios2_qsys interrupts and Jtag_uart interrupts are connected. The final completion effect is shown in 4.

Figure 4 Qsys Connections Completion effect

6, the relevant settings for the soft core. First double-click Nios2_qsys to enter the processor Setup module. Set the reset vector memory and Exception vector memory to onchip_memory.s1 under the core Nios II column.

7. Then, click System--Assign Base Addresses, and we'll see that the previous error in the lower messages window is all gone and changed to 0 errors,0 Warnings. If this is not the result, go back and follow the steps to check.

8, Next, click File--Save, save, here we save the file name is Nios_qsys.

9. Finally, select the Generation tab, set the Create simulation model to none, and then click Generate below to build. The time is long, everybody waits patiently. After the build is complete, click Close, and then close Qsys back to the Quartus II interface.

10. Double-click the blank space in BLOCK1.BDF to open the Symbol dialog box. Click Megawizard Plug-in Manager in the lower right corner, enter the macro module call interface, select Creat a new custom megafunction variation, click Next> to go to the next step, at what name do yo You want for the output file after the address to add the name of the export files, as the original content is

f:/fpgaandcpld/demo/nios/helloword_nios/,

Added to F:/fpgaandcpld/demo/nios/helloword_nios/pll_nios. Then search for ALTPLL in the search box on the right, select it, this step is to add the clock module to the system, then click Next> to proceed to the next step.

11, pop-up ALTPLL Settings dialog, here we are in the general column, what is the frequency of the inclk0 input? Place, change the clock to 50MHz, and then click Finish to complete the operation, A quartus II IP Files dialog box pops up, click Yes to complete and no action is required. Then click OK in the Symbol dialog box and place the module in BLOCK1.BDF.

12. Double-click Open Symbol dialog again, method with 10th step. Select Libraries-project–> Nios_qsys on the left and click OK to place the Nios_qsys in a blank space.

13. Double-click Open Symbol dialog again, method with 10th step. Enter input in name and the input signal icon appears on the right, and click OK to place it in an empty space. Repeat this step by adding a total of two inputs to the blanks, and then follow the same steps to add two inputs and gates (AND2) to the blanks.

14. Rename the two input signal icons to SYS_CLK and reset_n, and then display the connections as shown in Figure 5.

Figure 5 Connection diagram

15. Click File--Save to save the files with the name default, such as HELLOWORD.BDF.

16, click Assignments–> Pin Planner, add two node name SYS_CLK and Reset_n, the corresponding PIN is 28 and 112. Then close the Pin Planner dialog box.

17. Click Project, add/remove files in project ..., click the browse button after file name, select the. qsys file, click Add, and then click OK.

18, now to compile can. Click Processing, Start complilation, to compile. Compile time is too long, we wait patiently, after the download to the FPGA, the specific download process, here is not retrospective, we can refer to other information learning. Note: After downloading, do not power off, or download everything is lost , this is determined by the characteristics of the FPGA, you can learn for yourself.

At the end of the hardware section, the Software section is designed below.

19. Open Nios II 13.0 software Build Tools for Eclipse, first of all, need to make workspace Launcher (workspace) path settings, contact Eclipse Friends are familiar with, their own settings can be Note that the path does not contain spaces, etc. , and then click OK.

20, the new project. Click File, New, Nios II application and BSP from Template, which pops up the Nios II application and BSP from Template dialog box. Select the corresponding SOPC system first, click the browse button after Sopc information file name, select the soft core file that we have done in the previous hardware section, The suffix name is. Sopcinfo, it is important to note that the selected files must correspond, otherwise the system will fail because of a soft and hard mismatch. I choose the nios_qsys.sopcinfo here, then the system will automatically read the CPU name, we do not have to set up, the following fill out project name, here we fill

Written as Helloword, the project template uses the default. Then click Finish to finish. This will generate two project files in the Project Explorer on the left, as shown in 6.

Figure 6 The resulting project file

We hit Open Helloword project the following HELLO_WORD.C file, you can see the C language code, we add a sentence printf ("Hello word!  \ n "); Then, right-click on our Helloword project, select Nios II, BSP editor, enter the Nios II BSP editor configuration interface. We are mainly configured under the Main tab in Hall. The configuration details are shown in Figure 7. Then click Generate to generate the BSP library. When the build is complete, click Exit to quit.

21, the following we compile Helloword project. Right-click to select Build Project. The first compile, the time will be more frequent, wait patiently.

Figure 7 Nios II BSP Editor Configuration

22, after the completion of the compilation, right-click on the project, select Run as-Nios II Hardware, the Run Configurations dialog box, the Default Project tab in Project name and project ELF file The name should all have content, no choice. Then go to the Target Connection tab, and if there is nothing in connections, click on the Refresh connection on the right to find our downloader, and after we find it we click the System ID prroperties ..., System ID detection, check whether it is our previous set ID number, click Apply, then click on Run, this is the program will be automatically downloaded, and finally in the Nios II Console tab will show the results of the program run after downloading, that is, send back two words, the specific effect 8 shows.

Figure 8 Program Run effect

At this point, the entire experiment is over, congratulations on your last and successful completion of the task, refueling, juvenile!!

FPGA New Nios