FPGA Speed Grade

Altera's-6,-7,-8 speed level reverse order, Xilinx speed grade forward sort.

Not very strictly, "the lower the number, the higher the speed level" This is the Altera FPGA sorting method,

"The higher the serial number, the higher the speed level" is the Xilinx FPGA sorting method.

Since then, I have not been able to understand how the speed grade, the only concept is: the same chip can have multiple speeds, different speed levels represent different performance, different performance led to a huge difference in the price of the chip. There is always a vague speculation in the mind: FPGA manufacturers in order to improve profits, specifically to the same chip produced a different speed level.

Until a year ago and a colleague who had studied IC design hammer discussed this issue, there was a new understanding: for FPGA manufacturers, in order to get the same chip of different speed classes and special design of different chip layout is not cost-effective, so the chip speed level should not be specifically designed, And it should be after the chip production, the actual test calibration, the speed of the chip in the total output of the low ratio, the price is correspondingly high.

The answer was reasonable and corrected one of my misconceptions. But I still have two points of confusion: 1. What causes the performance difference of the same batch of chips; 2. If the factors are known, why not artificially control these factors, improve the production rate of high-speed chip, to increase the chip manufacturer's profits and reduce the price of high-speed chip.

A few days ago in the blog saw Hugu Friends of an FPGA speed grade, inspired me to further explore the above issues. By searching through the web, we get some understanding of the following steps:

1. The speed level of the chip is determined by the gate delay and line delay inside the chip, and these two factors depend on the length of the transistor and the capacitance C, the difference between the two values ultimately depends on the production process of the chip. I haven't found the answer to what kind of process has led to this discrepancy.

2. In the chip production process, there is a stage called speed binning. is to use a certain method, according to a set of standards for the production of chip screening and classification, and then divided into different speed levels. "Test and encapsulation" should include this process.

3. The calibration of the speed level depends not only on the quality of the chip itself, but also on the market positioning of the chip, rework probability and cost is also one of the factors.

4. Chip grades can be adjusted and improved after testing, which is widely used in the production of memory chips.

5. The process of chip production is full of variables, the production process can be controlled, but the control is not accurate to a molecule, an atom, product quality can only be a statistical goal. The chip on the same wafer will be different, even if the same chip has a variety of parts. The speed level is a statistic that reflects some of the common characteristics of a batch of chips and does not represent the quality of individual chips. And because some of the chip test is sampling, also does not rule out individual chip performance will be lower than the rated speed level. However, it is said that the FPGA test is very strict, it is likely that we have all the chips have been thoroughly tested. This is the reason that FPGA chip price is higher than ordinary chip.

Statistical Static Timing Analysis-a Better Alternative

6. The vast majority of the chips in the same class, the performance should be higher than the classification of the speed level standard. This is why in the FPGA design, there are a few timing analysis violations of the design of the download to the chip still able to work properly (the model parameters used in time series analysis are the statistical parameters of the chip, is the most conservative and safest). However, because the same level of chip still has performance differences, there is a timing violation but a single test of the successful FPGA design does not ensure that in the production of the individual chips do not have problems (the problem will be repaired or on-site investigation, the cost went up suddenly). Therefore, it is necessary to take the timing of convergence to be assured of mass production, which is the engineering standard of product quality assurance.

7. Probability and statistics originate from engineering practice, which plays a great guiding role in engineering practice. The standard in engineering practice is the accumulation of predecessors ' experiences and lessons, and it is the precious spiritual wealth of human society.

8. The real world is analog, not digital. When we look at real-world problems, our digital engineers and software engineers should abandon the concept of "one is 一、0 0" and see this continuous changing reality in a continuous way.

9. The uncertainty in the production process of the chip leads to the performance difference of the chip, which affects the price of the chip, the price and the performance of the compromise and affect our FPGA design engineers in the device selection, design methods of decision-making, we produce the product cost-effective determines the product sales, Product sales and determine the amount of chip procurement, purchasing volume and affect the purchase price of the chip .... Atomic, molecular-level differences, so that the first level of transmission and amplification. Human society is so interlocking, mutual restraint. Hey, that's amazing!

FPGA Speed Grade