FPGA static timing analysis-I/O port timing (input delay/output delay)

PDF download: http://files.cnblogs.com/linjie-swust/FPGA%E4%B8%ADIO%E6%97%B6%E5%BA%8F%E7%BA%A6%E6%9D%9F%E5%88%86%E6%9E%90.pdf1.1 Overview

In high-speed systems, FPGA timing constraints include not only internal clock constraints, but also complete Io timing constraints and timing exception constraints to achieve PCB-level timing convergence. Therefore, the timing constraints of the I/O ports are also important in FPGA timing constraints. Only when the constraints are correct can FPGA and external devices communicate correctly at high speed.

1.2 Overall FPGA Concept

Because I/O port Timing Constraint Analysis is for timing analysis of the entire system of the circuit board, FPGA needs to be used as a whole analysis, including FPGA creation time, holding time, and transmission latency. The traditional setup time, retention time, and transmission latency are all in the form of Register analysis. However, the Creation Time of FPGA for the entire system can be simplified.

 

Figure 1.1 overall FPGA Timing Diagram

1.1 shows the performance parameters of the decomposed FPGA internal register:

(1) tdin is the latency from the fpga I/O port to the FPGA internal register input;

(2) tclk is the latency from fpga I/O port to FPGA internal register clock end;

(3) tus/Th indicates the establishment time and retention time of FPGA internal registers;

(4) TCO indicates the FPGA internal register transfer time;

(5) tout is the latency from FPGA register output to IO port output;

For FPGA system analysis, You can redefine these parameters: FPGA creation time can be defined:

(1) FPGA Creation Time: ftsu = tdin + Tsu-tclk;

(2) FPGA holding time: FTH = TH + tclk;

(3) FPGA data transmission time: ftco = tclk + TCO + tout;

I/O timing analysis can be performed after FPGA becomes a system. The FPGA model becomes 1.2.

 

Figure 1.2 FPGA system parameters

1.3 maximum and minimum input latency

External devices send data to FPGA system model 1.3. The maximum and minimum input latency constraint for fpga I/O ports is to enable FPGA design tools to optimize the path latency from the input port to the first register as much as possible, this ensures reliable acquisition of signals from external chips to FPGA by the system clock.

Figure 1.3 FPGA data input model

The input delay is the delay time from the external device to the FPGA input port. This includes the latency from the clock source to the FPGA, the latency from the external device, the TCO of data transmission from the external device, and the cabling latency on the PCB. As shown in Figure 1.4, It is the timing of the external device and FPGA interface.

 

Figure 1.4 timing of external devices and FPGA Interfaces

1. maximum input latency

The maximum input latency (TCO) is the maximum output latency (TCO) of a device when the data transmission clock edge (lanuch edge) goes through the maximum external device clock skew (tclk1 ), in addition, the maximum PCB cabling latency (tpcb) can also be guaranteed when the minimum FPGA clock offset (ftsu) is subtracted. In this way, the FPGA creation time can be ensured and the data value can be accurately collected. That is, the setup slack must be positive, as shown in 1.1. The formula is as follows:

Setup slack = (tclk + tclk2 (min)-(tclk1 (max) + TCO (max) + tpcb (max) + ftsu) ≥ 0

The following formula is introduced:

Tclk1 (max) + TCO (max) + tpcb (max)-tclk2 (min) ≤ tclk + ftsu

According to the official data manual of Altera:

Input delay max = board delay (max)-board clock skew (min) + TCO (max)

The system parameter formula is as follows:

Input delay max = tpcb (max)-(tclk2 (min)-tclk1 (max) + TCO (max)

2. Minimum input latency

The minimum input latency (input delay min) is the minimum output latency (TCO) of the device when the data transmission clock edge (lanuch edge) goes through the minimum external device clock skew (tclk1 ), coupled with the minimum PCB cabling latency (tpcb), the total time delay value must be greater than the sum of the maximum FPGA clock latency and build time, in this way, the retention time of the last FPGA data is not damaged, that is, the hold slack must be positive, as shown in 1.1. The formula is as follows:

Hold slack = (tclk1 (min) + TCO (min) + tpcb (min)-(FTH + tclk2 (max) ≥ 0

The following formula is introduced:

Tclk1 (min) + TCO (min) + tpcb (min)-tclk2 (max) ≥ FTH

According to the official data manual of Altera:

Input delay max = board delay (min)-board clock skew (min) + TCO (min)

The system parameter formula is as follows:

Input delay max = tpcb (min)-(tclk2 (max)-tclk1 (min) + TCO (min)

We know from formulas 4 and 8 that we need to estimate the maximum and minimum latencies of input:

(1) the output data of the External Device reaches the maximum and minimum values of the FPGA port through the PCB. The latency experience of the PCB is 600mil/NS, 1mm = 39.37mil;

(2) maximum and minimum TCO of the output data delay after the external device receives the clock signal;

(3) maximum and minimum clock skew tclk1 when the clock source reaches the external device;

(4) the maximum and minimum clock skew tclk2 when the clock source reaches the FPGA;

When the external device clock is provided by FPGA, tclk1 and tclk2 are synthesized into tshew, as shown in Figure 1.5:

 

Figure 1.5 FPGA output clock Model

1.4 maximum and minimum output latency

FPGA outputs data to external device model 1.6. The maximum and minimum latency constraint on the output of fpga I/O ports is to enable FPGA design tools to optimize the path latency from the first register to the output port as much as possible, this ensures that external devices can accurately collect FPGA output data.

Figure 1.6 FPGA output delay model

The output delay is the delay time when the data is output from FPGA to the external device. This includes the latency between the clock source and FPGA, the latency from the external device, the cabling latency on the PCB, and the data creation and retention time of the external device. Shows the sequence diagram of FPGA and external device interfaces.

 

Figure 1.7 FPGA output latency

1. maximum output latency

According to the official data manual of Altera:

Output delay max = board delay (max)-board clock skew (min) + Tsu

According to the formula, the maximum output delay Max is the maximum PCB latency after FPGA data is sent, the minimum FPGA and the device clock skew, plus the creation time of the external device. The maximum output latency is restricted to restrict the output of the IO port, so that the data creation time of the external device is set, that is, the setup slack must be positive. The formula is as follows:

Setup slack = (tclk + tclk2 (min)-(tclk1 (max) + ftco (max) + tpcb (max) + TSU) ≥ 0

The following formula is derived:

Ftco (max) + tpcb (max)-(tclk2 (min)-tclk1 (max) + Tsu ≤ tclk

Then, the following formula is obtained:

Ftco (max) + output delay Max ≤ tclk

It can be seen that the maximum output latency is the maximum ftco value of the notification compiler FPGA. The correct comprehensive result is returned based on this value.

2. Minimum output latency

According to the official data manual of Altera:

Output delay min = board delay (min)-board clock skew (max)-th

According to the formula, the minimum output delay (output delay min) is the minimum PCB latency, the maximum FPGA and device clock skew after FPGA data is sent, and then the external device creation time is subtracted. The minimum output delay is restricted to restrict the output of the IO port, so that the output of the IO port has a minimum delay value. This prevents the output from being too fast and destroys the data retention time of the clock on the external device, as a result, the hlevels slack is negative and cannot be properly stored in the data. The formula for deriving the minimum output latency is as follows:

Hold slack = (tclk1 (min) + ftco (min) + tpcb (min)-(TH + tclk2 (max) ≥ 0

The following formula is derived:

Ftco (min) + tpcb (min)-(tclk2 (max)-tclk1 (min)-th ≥ 0

Then, the following formula is obtained:

Ftco (min) + output delay min ≥ 0

According to the formula, the maximum latency of the output is the minimum ftco value of the notification compiler FPGA. A correct comprehensive result is obtained based on this value.

We know from formulas 10 and 14 that we need to estimate the maximum and minimum latencies of the output:

(1) FPGA output data reaches the maximum and minimum values of the external device input ports through the PCB. The PCB latency experience is 600mil/NS, 1mm = 39.37mil;

(2) maximum and minimum clock skew tclk2 when the clock source reaches the external device;

(3) maximum and minimum clock skew tclk1 when the clock source reaches FPGA;

(4) establishment time Tsu and retention time th of the external device;

When the external device clock is provided by FPGA, tclk1 and tclk2 are synthesized into tshew, as shown in Figure 1.8:

Figure 1.8 FPGA provides a clock Model

1.5 scope of use

Based on the author's usage summary, I/O port timing constraints are mainly used in the following situations:

1. Frequent data exchange

Due to the IO time series constraints, the computing values are generally several nanoseconds. When FPGA and external data exchange frequency is low, such as FPGA operating 640*480 tft LCD screen flushing, the data transmission frequency is only 24 MHz, each data clock has a 41.666ns, which can meet the timing requirements without any constraints. However, when the operation of SDRAM runs to M, because a data transformation cycle is 8ns, a small delay of the IO port will affect the data of the SDRAM, in this case, complete IO port timing constraints must be imposed on the input and output, and the analysis is correct to eliminate data transmission instability.

2. The Code has been optimized.

When the data exchange frequency is high, but the time sequence constraints still do not meet the time sequence requirements, we all need to analyze the code. Good time sequences are designed, not constrained. As shown in program list 1.1, hcount_r and vcount_r are both 10-bit counters, so the three-color output port of code TFT will have a great delay, because there are too many bonding logics for dat_act, the output path is too long. In this case, it should not be the first time series constraint, but the code should be modified to achieve direct output of registers as much as possible. Only when the code is optimized and time series constraints are executed can better results be obtained.

Program list 1.1 example Program

1 assign dat_act  =    ((hcount_r >= hdat_begin) && (hcount_r < hdat_end))              　　 
2 　　　　　　　　　　 && ((vcount_r >= vdat_begin) && (vcount_r < vdat_end));
3 assign tft_r    =    (dat_act) ? {rgb16_dat[15:11], 3'b111} : 8'h00;
4 assign tft_g    =    (dat_act) ? {rgb16_dat[10:5],  3'b111} : 8'h00;  
5 assign tft_b    =    (dat_act) ? {rgb16_dat[4:0],   3'b111} : 8'h00; 

1.6 conclusion

This document mainly analyzes the timing constraints of fpga I/O ports, and does not analyze the actual usage. In the subsequent documents, we will combine the software, and the actual cases to introduce the timing constraints of the IO port in detail. The following is an example of the IO time series Constraint analysis provided by Altera, as shown in Figure 1.9.

 

Figure 1.9 Altera official routine