"FPGA whole Step----practical Walkthrough" The second chapter of the system construction

1 System Solutions

For the design of a hardware platform, the first to determine the overall framework to determine the requirements of each module chip and voltage distribution. Figure 2.6 is the hardware platform system that I have designed.

Figure 2.6 System block diagram

After selecting a system scheme, the next step is to look at the data sheet of the selected chip. Then look at the manual a few points must be noted, (1) The working voltage of the FPGA, determine if the FPGA work requires a few files of voltage, good design power circuit, (2) considering the power consumption, which determines the need for multi-power power to drive the chip to work properly; (3) View the distribution of the clock network, This determines the problem of clock allocation during logical design, (4) The JTAG download circuit, which is the key to determining the success of the data configuration, and (5) viewing the maximum frequency of the device's operation, which determines how much bandwidth the system can run.

For the calculation part of the power dissipation, it is necessary to find a vast project at the highest clock frequency of the system, calculate the consumed current portion, and then see if the theoretical value of the power supply circuit is designed to meet the demand for power dissipation. Because the FPGA core consumption is large, so design power circuit should be based on the core power consumption, that is, the 1.2V core consumes more than 3.3V I/O consumption,

2 FPGA Chip determination

For the determination of FPGA chips and the production of the back PCB, we need to look at Altera's official manual, which is designed from the manual. The manual is broadly divided into several parts: (1) Cyclone XX member overview, (2) Logical unit and logical array block, (3) storage unit, (4) Embedded multiplier resource, (5) Clock network resource, (6) I/O characteristics, (7) power-on Reset feature, (8) Jtag download;

Cyclone series chips are shown in table 2.1:

Because the cyclone series of films are not cheap, a piece of dozens of, so do not ask the most expensive, but resources can be enough. Compare resource situation, sourcing, price situation, choose Cyclone III ep3c5e144c8n. More detailed resources Please check the relevant manuals, design from the manual.

For the selected model, we should have a qualitative understanding. When we get a chip, we can roughly estimate the information of this chip, figure 2.7 is the information explanation of the chip model.

Figure 2.7 Chip Model description

For our chosen chip signal Cyclone III ep3c5e144c8n, the information expressed is:

One of the parameter information in the above model is the speed level, what does that mean? I am full of curiosity about things, search for relevant information, summarized as follows:

(1) For Altera chip, the lower the serial number, the higher the speed level, the more expensive the film. Speed: C6 > C7 > C8;xilinx speed Grading is the opposite of Altera;

(2) Each speed grade division is the production of the film after the test, fast marked with a low serial number, slow marking high serial number;

(3) The speed of the selection of the level, in line with the principle of sufficient, can use the slow is slow. Fast chip prices are high, not easy to buy.

Therefore, for the speed level, you can choose the C8 level, which is commonly used on the market level. If the timing is not satisfied, the time-series convergence problem can be achieved through high-quality Verilog code.

3 SDRAM Chip determination

Based on price, compatibility analysis, select several commonly used SDRAM chip, such as Hynix Company's hy57v641620et-6,hy57v283220t-6,hy57v2562gtr-75c, and Issi Company's Is42s1632b-7til ( Terasic Development Board used above), as well as Micron Company's products mt48lc8m32b2tg-6, the above several products in addition to the capacity and the width of the inconsistency, operation timing is the same. More detailed information can be found in the manuals section of the SDRAM folder.

SDRAM circuit part is simpler, PCB layout can not guarantee strict line length, but also not too long, otherwise it will cause signal delay, for the timing may not be able to meet the requirements. Figure 2.8 is a common circuit design scheme. It is also important to note that SD_CLK, the pin needs to be connected to the FPGA's pllx_clkoutn pin, in order to obtain a lower delay, more stable and reliable clock signal, and SDRAM clock up to 100MHz, so it is necessary to use this pin. You can view the pin_out pin file of the ep3c5e in detail.

Figure 2.8 SDRAM circuit

4 power supply each parameter determination

For the power supply section, see the manual xx shown, where vccint = 1.2v,vcca = 2.5V,VCCD_PLL = 1.2V, for IO voltage select commonly used 3.3V, Vio = 3.3V.

Figure 2.9 Electrical Characteristics

For FPGAs, high-quality power output is very important, which is related to the stability of the system. TI's official website gives some solutions to the FPGA, 2.10 shows the current situation in the FPGA, to see that the part that occupies the larger current is the kernel consumption. In Quartus II There are also pre-analysis power Tools-powerplay power Analyzer tool, if you have a larger project on hand, you can test the burn, the power consumption of the pre-test. For the 9v&1.3a (11.7W) power adapter on the DE2-35 platform, the 12v&3.5a power adapter is given on the DE1-SOC platform, so it is more than enough to use a general 2A or 1 a power adapter. There are two concepts in power supply design that are important, one is the Ldo, the other is DC, and the difference between the Ldo and the DC is explained below.

An LDO is a linear regulator that DC-DC (to) DC (the conversion of different DC power values), such as the input voltage and output voltage is very close, it is best to choose the ldo regulator , can achieve high efficiency. So, most of the applications that convert lithium-ion battery voltages to 3V output voltages are LDO regulators. Although 10% of the battery's energy is not in use, the Ldo regulator is still able to keep the battery working longer and with less noise. If the input voltage and output voltage is not very close, it is necessary to consider switching type of DCDC, because from the above principle can be known that the Ldo input current is basically equal to the output current, if the pressure drop is too large, the energy consumption on the Ldo is too high, inefficient. DC-to converters include boost, buck, liter/buck, and anti-equivalence circuitry. the advantages of a DC-to converter are high efficiency, large current output, and low quiescent current. With the increase in integration, many new-DC converters require only a few external inductors and filter capacitors. However, the output pulsation and switching noise of this kind of power controller are higher and the cost is relatively high. In general, the boost is a must to choose DCDC, Buck, is the choice of DCDC or Ldo, in terms of cost, efficiency, noise and performance comparison.

Differential pressure dropout, noise noise, power supply rejection ratio (PSRR), quiescent current IQ, which is the four key data for LDOs. The higher the PSRR, the lower the Ldo output ripple. IQ is the chip itself consumes the current, should try to choose a small IQ.

Figure 2.10 Ti on FPGA chip voltage and current analysis

For the design of the power supply section, using the following solutions, for only 3.3V and 1.2V power supply design, you can use the circuit shown in Figure 2.11. Here the D1 uses a 5.1V voltage regulator diode (for clamping), to prevent short-circuit, to prevent the external input voltage is too high and burn the circuits! The 3.3V and 1.2V voltages up to 3 A can be achieved with two parallel DC- Of course, for the commonly used AMS1117 chip, is based on the Ldo, but also can be used, but the current maximum seems to reach only 1 A, for some high-power occasions may need to reconsider, but the general situation should be able to adapt. For the Cyclone III after the addition of 2.5V voltage, you can imitate the above circuit to generate 2.5V, 2.12, only need to modify the MP chip output FB two resistance values can be. In addition to the above solutions, you can also choose power-specific chips such as TI's TPS75003 is also a good choice, if the cost is not very sensitive circumstances.

Figure 2.11 Power supply design

5 Download and Configuration circuit determination

For the configuration circuit part, need to consider the factors are also more, PCB layout is one side, then the Flash chip selection also need to pay extra attention. Figure 2.12 is a ep3c5 internal resource situation. Then when choosing EPCs chip, 2.13, its memory data must be larger than the internal resources of EP3C5, otherwise it may cause the storage to be unsuccessful. In doing nios also need larger memory EPCs, can choose EPCS16.

Official data above gives the EPCS and FPGA connection mode, 2.14, note that the data of the matching resistor can be in accordance with the official website above the 25ω, usually connected to a 33R, pay attention to Status,conf_done and nconfig pull-up resistor, It is necessary to strictly follow the official network specified circuit, otherwise it is possible that the download is unsuccessful. Here the configuration as mode, the clock maximum can reach 40MHz. As shown in 2.15. JTAG and FPGA Access section 2.16, the use of Vcca dedicated 2.5V voltage to power supply, this needs to be noted, and the TMS and TDI pull-up resistor, TCK in the pull-down resistor, JTAG is a popular way to download, more instructions can view the files in the Jtag folder.

Download the circuit section and the Configuration Circuit section of the total access Figure 2.17, add a configuration led, you can observe the download situation at any time. Due to the use of the as mode, note the configuration of Msel, shown in 2.18.

Figure 2.12 EP3CS5 Configuration Data volume

Figure 2.13 EPCS4 supported memory

Figure 2.14 EPCs and FPGA communication

Figure 2.15 EPCs communication with FPGA maximum clock frequency

Figure 2.16 Jtag and FPGA communication

Figure 2.17 Download and configuration circuit

Figure 2.18 Msel configuration in as mode

6 crystal oscillator and reset and PLL circuit determination

Crystal oscillator with active crystal 50MHz, access to 3.3V voltage and coupled with a decoupling capacitor, access to the FPGA's dedicated clock pin. Because the clock and reset need to walk the global Clock Network, has reached the clock signal delay to achieve the minimum.

Reset circuit here according to the manual above the input voltage over the threshold voltage of 1.7V, the 2.18,FPGA chip will begin to configure the logic, configuration time depends on the logical resources of how much. For the above configuration circuit, in the as mode, up to 40MHz, the lowest 20MHz, the corresponding period is 20ns~50ns, corresponding to the worst case needs to be a bit x 50ns/bit = 150ms, then the tolerance reset time t = RC x ln[(vi–v0)/( VI–VT)], for VI = 3.3V Vt = 1.7v,v0 = 0 case, t = 0.7239RC; for the selected r = 47k,c = 10μf, get t = 0.34s, greater than the FPGA reset power-up time. The input terminal of the PLL circuit is connected in parallel with the 10μf,0.1μf capacitor, and a clean PLL power input is obtained. Figure 2.20 is the entire Circuit diagram section.

Figure 2.19 EP3C5 Characteristics

Figure 2.20 Resetting the crystal oscillator and the PLL circuit section

"FPGA whole Step----practical Walkthrough" The second chapter of the system construction