Freescale mx27 DDR initialization code analysis

Before ddr sdram can be accessed, it must be initialized. The initialization process is pre-defined and incorrect operations will lead to unexpected results. During initialization, general mode registers and extended mode registers of ddrsdram will be set to define how ddr sdram works. These settings include burst length, burst type, CAS latency and working mode, as well as settings for ddr sdram internal DLL enabling and output driving capabilities in the extended mode register. The Mode register can be re-programmed. In this case, all the zones (banks) of the ddr sdram need to be idle, thus changing the memory working mode. If the operation is correct, re-programming the mode register will not change the data stored in the memory. After the initialization is complete, the ddr sdram enters the normal working state, and the memory can be read and written and refreshed.

The following code is taken from the DDR initialization code of mx27 Redboot. The hardware uses two hyb18m512160af chips to form 32bit memory width:

. Macro setup_sdram_ddr
LDR r0, soc_esdctl_base_w
MoV R2, # soc_csd0_base // 0xa0000000
MoV R1, #0x8 // initial Reset
// Lpddr delay line is reset.
STR R1, [r0, #0x10] // 0xd8001010 enhanced SDRAM control register 0
// Hold for more than 200ns
LDR R1, = 0x10000
1:
Subs R1, R1, #0x1
BNE 1b

MoV R1, #0x4
STR R1, [r0, #0x10] // 0xd8001010

// Check the chip version to1 or to2
LDR R1, soc_si_id_reg_w
LDR R1, [R1]
ANDS R1, R1, #0xf0000000
// Add latency on cas only for to2
// To 1.0's id = 0x0 ==>> CAS = 3
BNE 2f
LDR R1, sdram_0x00795729
B 3f
// Now handles to 2.x
2:
ANDS R1, R1, #0xe0000000
// To 2.0's id = 0x1 => CAS = 4 due to the MPEG4 issue
Ldreq R1, sdram_0x00795429
// TCAS [9: 8] = 2 clocks SDR and lpddr sdram cas latency2
// Subesquent to's are OK w/CAS = 3
Ldrne R1, sdram_0x00795729

// Set parameters such as TCAS tras trcd
// [31: 23] Reserved
// Txp [22: 21 = 4 clocks
// Twtr [20] = 2 clocks
// TRP [19: 18] = 3 clocks
// Tmrd [17: 16] = 2 clocks
// Twr [15] = srram 1 clocks; lpddr 2 clocks
// Tras [14: 12] = 6 clocks
// Trrd [11: 10] = 2 clocks
// TCAS [9: 8] = 3 clocks SDR and lpddr sdram cas latency2
// [7] Reserved
// Trcd [6: 4] = 3 clocks
// TRC [3: 0] = 10 clocks
3:
STR R1, [r0, #0x4] // 0xd8001004
LDR R1, sdram_0x92200000
// [31] SDRAM Controller enable
// [30-28] SDRAM Controller operating mode 001 = precharge command
// [27] supervisor protect
// [26:24] row address width 010-13 row addresses
// [23: 22] Reserved
// [21:20] column address width 10-10 column addresses

STR R1, [r0, #0x0] // 0xd8001000
LDR R1, [R2, #0xf00]
LDR R1, sdram_0xa2200000
// [31] SDRAM Controller enable
// [30-28] SDRAM Controller operating mode 010 = auto-Refresh command
// [27] supervisor protect
// [26:24] row address width 010-13 row addresses
// [23: 22] Reserved
// [21:20] column address width 10-10 column addresses
STR R1, [r0, #0x0]
LDR R1, [R2, #0xf00]
LDR R1, [R2, #0xf00]
LDR R1, sdram_0xb2200000
// [31] SDRAM Controller enable
// [30-28] SDRAM Controller operating mode 011 = load mode register command
// [27] supervisor protect
// [26:24] row address width 010-13 row addresses
// [23: 22] Reserved
// [21:20] column address width 10-10 column addresses
STR R1, [r0, #0x0]
Ldrb R1, [R2, #0x33]
Add R3, R2, #0x1000000
Ldrb R1, [R3]
LDR R1, sdram_0x82228133
// [31] SDRAM Controller enable
// [30-28] SDRAM Controller operating mode 000-normal read/write
// [27] supervisor protect
// [26:24] row address width 010 = 13 row addresses
// [23: 22] Reserved
// [21:20] column address width 10 = 10 column addresses
// [17: 16] SDRAM memory data width 10 = 32-Bit Memory width
// [] SDRAM refresh rate-Table 18-9. 100 = 8 clocks
// [11: 10] power down timer-Table 18-10. 01 = any time no banks are active
// [8] Full page-this bit shocould be set to 1 if the burst length
// The SDRAM connected to the CSD has been configured to full-page mode.
// [7] burst length. 1 = 8
// [] Precharge timer.-Table 18-12. 000101 = 10 clocks to precharge
STR R1, [r0, #0x0] // 0xd8001000
. Endm // setup_sdram_ddr