Frequency and hold time,gitter and hold Time

a . the effect of Setup time and hold time on frequency

Setup time and hold up time are determined by the device cell, typically less than 1~2ns, and do not change as the circuit design changes.

The clock frequency calculation method is as follows: without regard to the clock delay jitter and other conditions, ideally, a signal from the D end of the trigger to the Q end of the delay hypothesis is Tcell, from the Q end will pass through the combinational logic circuit combinational logic or network delay called Tdata , after the tdata signal will reach the next trigger D end, and must meet the trigger settling time tsetup.

Need to meet:

Tcd+tdelay+tsetup<=t

Otherwise the data cannot penetrate the next trigger, and it enters the metastable state.

The clock frequency f=1/t, the shorter the period frequency higher, the shortest period tmin= tcell+tdata+tsetup. and Tcell and Tsetup are determined by the device, the only thing we can reduce is tdata, in the circuit tdata there are many, the longest path (the critical path critical path) directly determines how fast the frequency can run. Therefore, timing optimization is always done from the critical path critical path.

In turn, setup time and hold time also have a binding effect on tdata.
In the actual design if the frequency is given, the design must also ensure that performance requirements. In this case,

Tcell+tdata+tsetup<=t is to be satisfied, so setup time determines the upper limit of the longest path.

The Tcell+tdata>=thold is also satisfied, and hold time determines the lower limit of the shortest path.

Specifically to SDC, this primary and output constraints are related, see <sta for nanometer design>capter 7 in section 7.5.

Summary: Ideally,the minimum value of the setup time constraint frequency after the main frequency is given, the maximum value of the hold time constraint frequency. The frequency is mainly determined by the tdata when the clock is not given .

two . Jitter The effect on the frequency

I've seen a definition of jitter there are two versions, essentially the same:

(1) The deviation from the ideal timing of the clock transition events

(2) A window within which a clock edge can occur

The effect of jitter on frequency is as follows:

Frequency and hold time,gitter and hold Time