From RTL view to Verilog language-turn to Cola Bean original

From RTL view to Verilog language

Once heard that a certain Daniel said: "When you learn the FPGA to a realm, you see the hardware description language, will no longer be a simple language, but by a logic door composed of the circuit diagram, once reached this realm, can write code to the extreme!" ”

The author is how to hope to achieve this realm AH ~ ~, but this realm to the author's feeling is so illusory.

Some time ago I wrote a blog titled "Error-prone analysis of FPGA (Verilog) level detection module". I looked closely at the Verilog corresponding RTL view, and the RTL view and Verilog contrast, suddenly a little sentiment.

First of all in the author's own hand-drawn logic diagram, hehe ~ ~ Please forgive its ugliness. Can the reader directly imagine the Verilog from the graph?

On the left side of the dotted line: there is an input a port, input clock, reset signal and a D trigger.

To the right of the dotted line: there are two non-gates and two with doors, and two output ports.

The output of the combinational logic is directly related to the input, and the output of the timing logic is also related to the original state.

So the diagram on the left is what we often call time-series logic, and the right-hand graph is the combinatorial logic.

First look at the right view, see if can think of it as Verilog, Yi, it seems not difficult-not just a few input through a few non-door and with the door. Suppose the input is called F1 and F2.

So for the upper part of the right view of the graph:

Wire Neg_edge =! F1 & F2;

So for the upper part of the right view of the graph:

Wire Pos_edge = F1 &! F2;

Looking at the sequential logical view on the left, we find that the F1 is related to the F2 timing, F1 is directly connected to the input of the D trigger, and F2 is directly connected to the output of the D trigger. For D triggers, from the input to the output, from the start edge to the latch edge.

The interval between F1 and F2 is exactly a clock cycle (regardless of the physical delay).

Well, the relationship between F1 and F2, we also found. Now try to write the Verilog timing logic according to the logical view of the left-hand sequence. Try it, it seems not difficult.

Always @ (Posedge CLK)//Timing logic must have clocks, right ~

Begin

F1 <= A; F1 directly connected to the input a port

F2 <= F1; F2 and F1 are separated by a clock cycle

End

Finally, let's look at the whole picture and imagine the Verilog code in the brain, and the results appear.

Always @ (Posedge CLK or Negedge rstn)

if (! RSTN) begin F1 <= 1 ' b0; F2 <= 1 ' b0; end//plus an asynchronous reset

Else

Begin

F1 <= A; F1 directly connected to the input a port

F2 <= F1; F2 and F1 are separated by a clock cycle

End

Wire Neg_edge =! F1 & F2;

Wire Pos_edge = F1 &! F2;

Now to the author's feeling, is not need to memorize this level detection module, because of a daze, the author's head seems to emerge a picture, this picture in the guide this author how to write this module.

In fact, there is a better way to remember:

F1 current STATE;F2 Previous State,

So! F1 & F2 = = 1 must be the previous value is 1, now the value is 0, then the nature of detection is the falling edge.

Similarly: F1 &! F2 = = 1 must be the previous value is 0, now the value is 1, then the nature of detection is the rising edge.

Summary: From see Verilog can reflect the logical view (RTL), I feel very difficult, this requires a lot of experience accumulation, on the contrary, from see the logical view can reflect the Verilog, I feel relatively easy. If we start from the easy, slowly accumulate experience. Maybe one day can reach the realm that Daniel said, haha ~ ~

2013-11-12

--Song Huan

From RTL view to Verilog language-turn to Cola Bean original