FSMC of stm32

Previously Used stm32f103rbt6, which is within 100 pins without FSMC. It is troublesome to write timing programs on the LCD screen or SRAM. Later it was changed to stm32f103zet6 with FSMC. However, I encountered a problem when learning FSMC.

I didn't understand the last two sentences at first. Later I checked some materials and finally understood them.

First of all, I would like to explain some common knowledge: The address bus width only indicates the CPU addressing range, which has nothing to do with the number of cpus. That is to say, the 32-bit CPU address line is not necessarily 32.

FSMC addressing of stm32 is in bytes, that is to say, if you define a 16-Bit Array, for example, 00000000 temp [5], if the temp address is 0x00000002, then the temp + 1 address is 0 x (the address is plus 2)
Is62wv51216 is a 16-bit bandwidth of KB, that is, one of its addresses corresponds to two bytes, but stm32 is an address and one byte, which leads to the issue of targeting. If our address line is still 2017a0 ~ A15 and memory a0 ~ A15 connection. If the stm32 needs to read the temp [1] in the previously mentioned array from the SRAM, Stm32 will provide 0x0002 (binary address 20171000000000010b), but for our SRAM, we read temp [2], because an address of SRAM is a 16-bit data. To solve this problem, we only need to shift one bit to the right when sending the address to the SRAM (one address of the SRAM corresponds to the data of the stm32 addresses ).
To provide convenience for users, if you select a 16-bit-width sram fsmc, it will automatically perform one-bit right shift operation when you send the address.
In this case, another problem occurs: Is it useless to shift one A0 right each time? That is, can only read and write data from even addresses?
This is the role of nbl0 and nbl1. If you want to perform byte operations
For example, if the stm32 Sending address 0x0001 is used to read the 16-bit data at the SRAM address 0x0000, FSMC uses ao to control nblo and nbl1 to read the High-byte data at 10.
Therefore, only nbl0 is valid for reading and writing even bytes, and only nbl1 is valid for reading and writing odd bytes (low-level ).

Reference Source: http://www.openedv.com/posts/list/33759.htm