Function details of migrating dm9000 from wince5.0 to dm9000 register-reprinted

Http://www.rosoo.net/a/200911/7966.html dm9000 (a) is a fully integrated, powerful, cost-effective Fast Ethernet MAC controller, it has a general-purpose processor interface, an EEPROM interface, a 10/100 PHY and a 16 kb SRAM (13 KB as the receiving FIFO, 3 kb as the sending FIFO ). It uses a single power supply and is compatible with 3.3 V and 5 v io Interface levels.

Dm9000 (a) also supports the media independent interface (media-independent) interface to connect to hpna (home phone-line networking Alliance) devices or other devices that support MII.

Dm9000 (a) contains a series of accessible control status registers that are byte aligned and set to an initial value when the hardware or software is reset.

The following describes the register function of dm9000:

NCR (00 h): network control register)

7: ext_phy: 1 select External phy, 0 select internal phy, not affected by software reset.

6: wakeen: Event wake-up enabling, 1 enable, 0 disable and clear the event wake-up status, not affected by software reset.

5: Reserved.

4: fcol: 1 forced conflict mode, used for user testing.

3: fdx: full duplex mode. Read-only in internal PHY mode and read/write in external PHY mode.

2-1: LBK: loopback mode (loopback) 00 usually, 01mac internal loopback, 10 Internal phy m Digital loopback, 11 retained.

0: RST: 1 software reset, automatically cleared after 10 us.

NSR (01 H): Network Status Register)

7: Speed: Medium Speed. In the internal PHY mode, 0 is 100 Mbps, and 1 is 10 Mbps. This bit is not used when linkst is set to 0.

6: linkst: connection status. In the internal PHY mode, 0 indicates a connection failure, and 1 indicates a connection.

5: wakest: Wake up event status. Read or write 1 is cleared. It is not affected by software reset.

4: Reserved.

3: tx2end: TX (send) data packet 2 Completion mark. Write 1 will be cleared (the official Manual indicates that both read and write can be cleared, but after the experiment, only 1 can be cleared !). Data Packet pointer 2 is transmitted completely.

2: tx2end: TX (send) packet 1 Completion mark. Write 1 will be cleared (the official Manual indicates that both read and write can be cleared, but after the experiment, only 1 can be cleared !). Data Packet pointer 1 is transmitted completely.

1: rxov: rx (received) FIFO (first-in-first-out cache) overflow flag.

0: Reserved.

CTL (02 h): TX control register)

7: Reserved.

6: tjdis: jabber transmission enabled. 1 enable the jabber transmission timer (2048 bytes), 0 forbidden.

Note: Jabber is a long frame with a CRC error (larger than 1518bytes but less than 6000 bytes) or a packet restructuring error. Cause: it may cause network packet loss. Mostly because the workstation has hardware or software errors.

5: excecm: Extra conflict mode control. 0. If the number of conflict counts is greater than 15, the packet is terminated. 1 always tries to send this packet.

4: pad_dis2: do not add pad for data packet pointer 2.

3: crc_dis2: CRC verification is not allowed for data packet pointer 2.

2: pad_dis2: do not add pad for data packet pointer 1.

1: crc_dis2: CRC verification is not allowed for data packet pointer 1.

0: txreq: TX (send) request. This bit is automatically cleared after sending.

Tsr_ I (03 h): Send Status Register 1 (TX Status Register I) of packet pointer 1)

7: tjto: the jabber transmission times out. This position indicates that the data frame is truncated because more than 2048 bytes of data are transmitted.

6: LC: the carrier signal is lost. This position indicates that the red carrier signal is lost during frame transmission. This bit is invalid in internal loop mode.

5: NC: no carrier signal. This position indicates that there is no carrier signal during frame transmission. This bit is invalid in internal loop mode.

4: LC: Conflict delay. This position indicates that a conflict occurs again after the 64-byte conflict window.

3: Col: Packet Conflict. This location bit indicates a conflict occurred during transmission.

2: EC: additional conflicts. This location indicates that the transfer is terminated due to 16th conflict (that is, an additional conflict.

1-0: Reserved.

Tsr_ii (04 H): Send Status Register 2 (TX Status Register II) of data packet pointer 2)

Same as tsr_ I

.

RCR (05 h): RX control register)

7: Reserved.

6: wtdis: the watchdog timer is disabled. 1 forbidden, 0 enable.

5: dis_long: discard long data packets. 1 is to discard a packet with a length of more than 1522 bytes.

4: dis_crc: discard packets with incorrect CRC verification.

3: All: Ignore all multipoint transfers.

2: RUNT: Ignore incomplete data packets.

1: prmsc: promiscuous mode)

0: rxen: receive the enable.

RSR (06 h): receiving status register (RX Status Register)

7: RF: incomplete data frame. This position indicates that a frame smaller than 64 bytes is received.

6: MF: multi-point transmission frame. This position indicates that the received frame contains a multi-point transfer address.

5: LCs: Conflict delay. This position indicates a conflict delay during frame receiving.

4: rwto: receives timed overflow from the watchdog. This position indicates that a data frame larger than 2048 bytes is received.

3: ple: physical layer error. This position indicates that a physical layer error occurs during frame receiving.

2: AE: alignment ). This position indicates that the end of the received frame is not in byte alignment, that is, it is not in byte boundary alignment.

1: Ce: CRC verification error. This position indicates the received frame CRC verification error.

0: foe: receives FIFO cache overflow. This position indicates that the FIFO overflow occurs when the frame is received.

Rocr (07 h): receive overflow counter register)

7: rxfu: receives overflow counters. This position indicates that the ROC (receiving overflow counter) overflows.

6-0: ROC: receives overflow counters. This counter is a static counter, indicating the number of overflow packets received after the FIFO overflow.

Bptr (08 h): Back pressure threshold register (back pressure threshold register)

7-4: bphw: Maximum back pressure threshold value. When the free space of the received SRAM is lower than the threshold value, the Mac will generate a crowded state. 1 = 1 kb. The default value is 3 h, that is, 3 kb of free space. It must not exceed the SRAM size.

3-0: jpt: congestion time. The default value is 200us. 0000 is 5us, 0001 is 10us, 0010 is 15us, 0011 is 25us, 0100 is 50us, 0101 is 100us, 0110 is 150us, 0111 is 200us, 1000 is 250us, 1001 is 300us, 1010 is 350us, 1011 is 400us, 1100 is 450us, 1101 is 500us, 1110 is 550us, and 1111 is 600us.

Fctr (09 h): flow control threshold register)

7-4: hwot: maximum threshold for receiving FIFO cache overflow. When the free space of the received SRAM is less than the threshold value, a pause packet with the pause time (pause_time) as ffffh is sent. If the value is 0, no free space is received. 1 = 1 kb. The default value is 3 h, that is, 3 kb of free space. It must not exceed the SRAM size.

3-0: Lwot: minimum threshold for receiving FIFO cache overflow. When the free space of the received SRAM is greater than the threshold value, a pause packet with a pause time (pause_time) of running H is sent. When a paused packet with the highest overflow threshold is sent, the paused packet with the lowest overflow threshold is valid. The default value is 8 KB. It must not exceed the SRAM size.

Rtfcr (0ah): receiving/sending overflow control register (Rx/TX flow control register)

7: txp0: 1 send the pause packet. After sending the packet, it is automatically cleared and set the Tx pause package time to 0000 h.

6: txpf: 1. Send the pause packet. After sending the packet, it is automatically cleared and set the Tx pause package time to ffffh.

5: txpen: force the pause packet to enable. The maximum overflow threshold is used to enable sending of the pause packet.

4: bkpa: Back Pressure mode. This mode is only valid in half duplex mode. A Congestion State occurs when the received SRAM exceeds bphw and new packets are received.

3: BKPM: Back Pressure mode. This mode is only valid in half duplex mode. When the received SRAM exceeds the bphw and the data packet da matches, a congestion state is generated.

2: rxps: receives the paused package status. Read-Only resetting is allowed.

1: rxpcs: receives the current status of the paused package.

0: flce: overflow control enabled. 1. Set the Enable overflow control mode.

Epcr/phy_cr (0bh): EEPROM and PHY control register (EEPROM & PHY control register)

 

 

 

 

 

 

 

 

7-6: Reserved.

5: reep: Reload the EEPROM.DriverThe program needs to reset the bit after the operation is completed.

4: WEP: EEPROM write enabling.

3: EPOS: select a bit for the eeprom or PHY operation. 0: Select EEPROM; 1: Select Phy.

2: erprr: EEPROM read, or PHY register READ command. The driver needs to reset the bit after the operation is completed.

1: erprw: EEPROM write, or PHY register write command. The driver needs to reset the bit after the operation is completed.

0: erre: Access status of the eeprom or Phy. 1 indicates that the eeprom or PHY is being accessed.

Epar/phy_ar (0ch): EEPROM or PHY Address Register (EEPROM & PHY Address Register)

7-6: phy_adr: the lower two (bit1, bit0) of the PHY address, while the bit [] of the PHY address is forced to be 000. If you want to select an internal phy, set the two-digit value to 01, and set the value to 01 in actual applications.

5-0: eroa: The eeprom address or the PHY Register address.

Epdrl/phy_drl (0dh): EEPROM or PHY data register low half-byte (EEPROM & PHY low byte data register)

7-0: ee_phy_l

Epdrl/phy_drh (0eh): high half-byte (EEPROM & PHY high byte data register) of the eeprom or PHY data register)

7-0: ee_phy_h

Wucr (0fh): Wake up control register (wake up control register)

7-6: Reserved.

5: linken: 1 enables "connection status change" to wake up events. This bit is not affected by the software reset.

4: sampleen: 1 enables "sample frame" to wake up events. This bit is not affected by the software reset.

3: magicen: 1 enables "Magic packet" to wake up events. This bit is not affected by the software reset.

2: linkst: 1 indicates a connection change event and a connection status change event. This bit is not affected by the software reset.

1: samplest: 1 indicates that "sample frame" and "sample frame" events are received. This bit is not affected by the software reset.

0: magicst: 1 indicates that "Magic packet" and "Magic packet" events were received. This bit is not affected by the software reset.

PAR (10 h -- 15 h): physical address (MAC) Register (physical address register)

7-0: pad0 -- pad5: physical address byte 0 -- byte 5 (10 h -- 15 h ). It is used to store 6-byte MAC addresses.

Mar (16 h -- 1dh): multicast address register)

7-0: mab0 -- mab7: multipoint Sending address byte 0 -- byte 7 (16 h -- 1dh ).

GPCR (1fh): gpio control register (general purpose control register)

7-4: Reserved.

3-0: gep_cntl: gpio control. Defines the input and output directions of gpio. 1 indicates output, and 0 indicates input. By default, gpio0 provides the power_down function for output. Others are input by default. The default value is 0001.

GPR (1fh): gpio register (general purpose register)

7-4: Reserved.

3-1: GEPIO3-1: gpio for the output, the relevant bit control corresponding to the gpio port status, gpio for the input, the relevant bit reflects the corresponding gpio port status. (Similar to the single-chip microcomputer's control over the I/O port ).

0: gepio0: Same as above. This bit outputs 1 to the power_dewn internal PHY by default. If you want to enable the phy, the driver needs to reset the pwer_down signal by writing "0. The default value can be obtained through EEPROM programming. Refer to the description of EEPROM.

Trpal (22 h): Send an SRAM read pointer to a lower half byte (tx sram read pointer address low byte)

7-0: trpal

Trmep (23 h): Send the high half-byte read pointer address of the SRAM (tx sram read pointer address high byte)

7-0: TRPA

Rwpal (24 h): receives the low-half-byte SRAM pointer address (rx sram write pointer address low byte)

7-0: rwpal

Rwhpa (25 h): receives the high half byte of the SRAM pointer address (rx sram write pointer address high byte)

7-0: rwpa

Vid (28 h -- 29 H): manufacturer serial number (vendor ID)

7-0: vidl: low half-byte (28 h), read-only, 46 h by default.

7-0: vidh: high half-byte (29 H), read-only, default: 0ah.

PID (2ah -- 2bh): product serial number (product ID)

7-0: pidl: low half-byte (2ah), read-only, default 00 H.

7-0: pidh: high half-byte (2bh), read-only, 90 h by default.

Chipr (2ch): Chip Revision)

7-0: pidh: Read-only. The default value is 00 H.

Tcr2 (2dh): Transport Control register 2 (TX control register 2)

7: LED: led mode. 1. Set the LED pin to Mode 1 and 0. Set the LED pin to Mode 0 or based on the eeprom settings.

6: rlcp: 1 resend the packet with conflicting latency.

5: DTU: 1 do not resend the "underruned" packet.

4: onepm: Single-package mode. 1. The command to send a data packet before sending is executed, and the command to send more than two data packets before sending is executed.

3-0: ifgs: Specifies the interframe interval. 0xxx is 96bit, 1000 is 64bit, 1001 is 72bit, 1010 is 80bit, 1011 is 88bit, 1100 is 96bit, 1101 is 104bit, 1110 is 112bit, 1111 is 120bit.

OCR (2EH): Operation Control Register)

7-6: SCC: Set the internal system clock. 00 is 50 MHz, 01 is 20 MHz, 10 is 100 MHz, and 11 is retained.

5: Reserved.

4: SOE: internal SRAM output enabling is always enabled.

3: SCS: internal SRAM slices are always enabled.

2-0: phyop: Internal PHY operation mode for testing.

Smcr (2fh): Special mode control register (special mode control register)

7: sm_en: special mode enable.

6-3: Reserved.

2: FLC: Forced conflict delay.

1: Fb1: force the maximum "back-off" time.

0: fb0: force the shortest "back-off" time.

Etxcsr (30 h): Pre-transfer (early) control, Status Register (early transmit control/Status Register)

7: ete: Enable before transmission.

6: ets2: status 2 before transmission.

5: ets1: Status 1 before transmission.

4-2: Reserved.

1-0: Ett: transport front door limit. When the number of data bytes written to the sending FIFO cache reaches this threshold, transmission starts. 00 is 12.5%, 01 is 25%, 10 is 50%, 11 is 75%.

Tcscr (31 H): transmit check sum control register)

7-3: Reserved.

2: udpcse: UDP checksum generation enable.

1: tcpcse: TCP test and enable generation.

0: ipcse: Enable IP checksum generation.

Rcscsr (32 h): receive check sum control status register)

7: UDPS: UDP checksum status. 1 indicates that UDP packet Verification Failed.

6: TCPS: TCP checksum status. 1 indicates that TCP packet Verification Failed.

5: IPS: IP address checksum status. 1 indicates that IP packet Verification Failed.

4: udpp: 1 indicates UDP data packets.

3: TCPP: 1 indicates TCP data packets.

2: IPP: 1 indicates IP data packets.

1: rcsen: Receive, test, and enable. 1 enable checksum and verification, and store the checksum status bit (bit7-2) to the first byte of the respective packet header of the packet.

0: dcse: discards packets with incorrect checksum. 1. The packet with incorrect checksum is discarded. If the IP/TCP/UDP checksum and domain are incorrect, the packet is discarded.

Mr1200x (f0h): Read data command with the same memory address (memory data pre-Fetch READ command without address increment register)

7-0: mr1200x: read data from the received SRAM. After reading the data, the read pointer pointing to the internal SRAM remains unchanged.

Mr1_x1 (f1h): Memory read address unchanged read data command (memory data read command with address increment register

Same as above.

Mrcmd (f2h): Read data command automatically added to the memory read address (memory data read command with address increment register)

7-0: mrcmd: reads data from the received SRAM. After reading the data, the read pointer pointing to the internal SRAM is automatically increased by 1, 2, or 4, depends on the operating mode of the processor (8-bit, 16-bit, or 32-bit ).

Mrrl (f4h): Memory read address register low half-byte (memory data read _ address register low byte)

7-0: mdral

Mrrh (f5h): Memory read address register high half-byte memory data read _ address register high byte

7-0: mdrah: If bit7 of IMR is 1, this register is set to 0ch.

Mw1_x (f6h): Memory read address unchanged read data command (memory data write command without address increment register)

7-0: mwcmdx: write data to the sent SRAM, And the write address pointer pointing to the internal SRAM remains unchanged.

Mwcmd (f8h): Read data command automatically added to the memory read address (memory data write command with address increment register)

7-0: mwcmd: write data to the sent SRAM, and then automatically add 1, 2, or 4 to the read pointer pointing to the internal SRAM, depends on the operating mode of the processor (8-bit, 16-bit, or 32-bit ).

Mwrl (Fah): memory write address register (memory data write _ address register low byte)

7-0: mdral

Mwrh (FBH): memory write address register (memory data write _ address register high byte)

7-0: mdrah

Txpll (FCH): Send packet length register low half-byte (TX packet length low byte register)

7-0: txpll

Txplh (FDH): Send packet length register (TX packet length high byte register)

7-0: txplh

ISR (Feh): interrupt Status Register (Interrupt Status Register)

7-6: iomode: processor mode. 00 is in 16-Bit mode, 01 is in 32-Bit mode, 10 is in 8-Bit mode, and 11 is retained.

5: lnkchg: the connection status changes.

4: udrun: transmit "underrun"

3: Roos: receives overflow counters.

2: ROS: receive overflow.

1: PTS: data packet transmission.

0: PRS: receives data packets.

ISR register write 1 in each status clear

IMR (FFH): Interrupt Mask register)

7: par: 1 enables the pointer to automatically jump back. When the Read and Write pointer of an SRAM instance exceeds the upper limit of that of an SRAM instance, the pointer automatically jumps back to the starting position. The driver needs to set this bit. If this bit is set, reg_f5 (mdrah) will automatically set 0ch.

6: retain.

5: lnkchgi: 1 enables connection status change interruption.

4: udruni: 1 enables transmission of "underrun" interruptions.

3: Rooi: 1 enables receiving overflow counters.

2: ROI: 1 enables receiving overflow interruptions.

1: PTI: 1 enables a data packet transmission terminal.

0: PRI: 1 enables data packet reception to be interrupted.

 

 

 

Note: The "Blue font" indicates the registers to be used during dm9000 initialization.

The method to access the above registers is through the bus drive, that is, through the IOR, Iow, aen, CMD, SD0--SD15 and other related pin operations to achieve. The cmd pin is the write Register address when it is high, and the write data to the Register at the specified address when it is low. For detailed procedures, see the "read/write sequence" section in the Data Manual.

In dm9000 (A), there are some PHY registers, also known as the MII registers of the media-independent interface, which need to be accessed. These registers are word-aligned, that is, 16-bit width. The following lists three commonly used PHY registers.

Bmcr (00 h): Basic Mode Control Register)

15: Reset: 1phy software reset, 0 normal operation. Reset the value of the PHY register to the default value. After the reset operation is completed, this bit is automatically cleared.

14: loopback: 1loop-back enabled, 0 normal operation.

13: Speed Selection: 1 is 100 Mbps, and 0 is 10 Mbps. The connection speed can be selected based on this bit, or automatically negotiated based on the 12th bit. When automatic negotiation is enabled, that is, when the 12th bits are 1, this bits will return the speed value after automatic negotiation.

12: auto-negotiation enable: 1 automatic negotiation enabled. Make the values of 13th bits and 8th BITs reflect the status after automatic negotiation.

11: power down: power_down mode. 1 is power_down, and 0 is normal. In the power_down status, phy should respond to the operation. When it is changed to the power_down State or is already running in the power_down state, the PHY will not generate false signals on the MII.

10: isolate: 1 apart from some operations, phy will be isolated from MII, 0 is normal operation. When this position is set, phy does not respond to txd [], tx_en and tx_er input, and in tx_clk, rx_clk, rx_dv, rx_er, rxd [], col and CRS are output in high-impedance mode. When the PHY is isolated, it will respond to the operation.

9: restart auto-aegotiation: 1 reinitialize Automatic negotiationProtocol, 0 indicates normal operation. If this function is disabled by 12th bits, this bit is invalid. This bit is automatically cleared after initialization.

8: duplex mode: 1 indicates full duplex operation, and 0 indicates normal operation. When 12th bits are disabled (set to 0), this bits are set. If 12th bits are set, the BITs reflect the status after automatic negotiation.

7: collision test: 1 indicates the conflicting test enable, and 0 indicates the normal operation. If this position is set, the tx_en statement will cause the col signal to be declared.

6-0: Reserved.

ANAR (04 H): auto-negotiation advertisement register)

15: NP: 0 indicates that there is no valid next page, and 1 indicates that the next page is valid. The next page does not exist for phy, so this bit is always 0.

14: ACK: 1 indicates that the data of the connected object is received for authentication, and 0 indicates that no authentication is performed. The automatic negotiation status of PHY is automatically controlled by the opportunity.

13: RF: 1 indicates that the local device is in the error state, and 0 indicates no error check.

12-11: Reserved.

10: FCS: 1 indicates that the processor supports overflow control, and 0 indicates not.

9: T4: 1 indicates that the local device supports 100base-t4, and 0 indicates not. Phy does not support 100base-t4, so this bit is always 0.

8: tx_fdx: 1 indicates that the local device supports the full duplex mode of 100base-tx, and 0 indicates that the full duplex mode is not supported.

7: tx_hdx: 1 indicates that local devices support 100base-tx, and 0 indicates not.

_ Fdx: 1 indicates that the local device supports the full-duplex mode of 100base-t, and 0 indicates that the full-duplex mode is not supported.

_ Hdx: 1 indicates that local devices support 100base-t, and 0 indicates not.

4-0: selecter: The Protocol bit. 00001 is the default value, indicating that the device supports 802.3csma/CD and does not need to be modified.

Dscr (16 h): davicom detailed configuration register (davicom specified configuration register)

15: bp_4b5b: 1 is the function of bypassing 4b5b encoding and 5b4b decoding. 0 is the function of 4b5b and 5b4b.

14: bp_scr: 1 is the function of bypassing the disturbance frequency and cleaning, and 0 is the normal operation.

13: bp_align: 1 is used to bypass the scrambling, symbol queue, decoding, and symbol encoding and scrambling functions at the time of receiving. 0 is normal.

12: bp_adpok: 1 indicates the forced signal detection function, and 0 indicates the normal operation. This bit is only used for debugging.

11: Reserved.

10: TX: 1 indicates 100base-tx operation, and 0 is retained.

9-8: Reserved.

7: f_link_100: 0 is normal 100 Mbps, 1 is forced Mbps good connection status.

6-5: reserved, forced to 0.

4: RPDCTR-EN: 1 to enable automatic simplification power_down, 0 is disabled.

3: smrst: 1 is the state machine that reinitializes the phy. After initialization, this bit is automatically cleared.

2: mfpsc: 1 indicates that the MII frame boot suppression is enabled, and 0 indicates that the frame is disabled.

1: Sleep: sleep mode. This position will cause the PHY to enter sleep mode. by resetting the position, the sleep mode will be restored to the state before sleep mode, but the state machine will be reinitialized.

0: rlout: This location places the received data into the sending channel.

The method to access the PHY register is:

(1) Register address writingEpar/phy_ar (0ch)In the register, note that location 1 (address and 0x40) of the Register address must be set to 6th to indicate that the write is the PHY address, not the eeprom address.

(2) write data in high bytesPhy_drh (0eh)Register.

(3) Write low data bytesPhy_drl (0dh)Register.

(4) Send the PHY command (0x0a)Epcr/phy_cr (0bh)Register.

(5) send the command 0x08Epcr/phy_cr (0bh)In the register, clear the PHY write operation.

The above is a detailed description of the common register functions of dm9000 (a). By accessing these registers, we can perform initialization, data transmission, and receiving operations on dm9000. To implement ARP, IP, TCP, and other functions, you need to understand the relevant protocols, which can be achieved by writing related protocols or porting protocol stacks.