Further description of the pin in Altera FPGA

Recently, the great god of end China, a faint bean, published the blog fpga r & D path (25)-pin, I just got a new book titled deep understanding of Altera FPGA application design. Here we will organize the knowledge of the two. I/O feature notes for the cyclone IV device will be added later.

In the previous article, the pin introduction in Altera FPGA has provided a brief and comprehensive description of the pin in Altera FPGA. The following will provide some in-depth understanding.

1. Generally, it is recommended that DDR interface signals be constrained on one bank. If not, the control signals must be constrained on the same bank; otherwise, an error is reported in the layout and wiring of the EDA tool. It does not explain how to constrain to the same bank

 

2. Refer to the original words on the aobaodou blog:

1) For a set output signal, the level format is lvcoms, for example, set_instance_assignment-name io_standard lvcoms-to pin. There are no settings for pulling up or pulling down (that is to say, the COMs level does not include the setting of the up and down resistance ). However, you can set the output current, for example, set_instance_assignment-name current_strength_new 12ma-to pin-level circuit signal is not in place. In many cases, it is a problem with the driving capability. You can also set the output end's electrical resistance (not up/down ). Set_instance_assignment-name output_termination "series 50 ohm with calibration"-to pin and other attributes (2) You can set the up/down status for unrestrained signals. For example, set_global_assignment-name reserve_all_unused_pins "as input tri-stated with weak pull-up" the other states are as inputs that are tristated, as outputs that drive ground, as outputs that drive an unspecified signal, asinput tri-stated with bus-hold

 

3. the I/O port voltage cannot be specified through constraints. For example:

Set_instance_assignment-name io_standard3.0-V lvcmos-To Pina

Set_instance_assignment-name io_standard3.3-V lvcmos-To Pinb

This constraint does not work. The output voltage of I/O is only related to the reference voltage of the specified bank.

 

4. The differential signals of LVDS must be allocated to the same differential pipe foot, and the pad near LVDS cannot be used as a single-ended pin, as to how many pads are needed for single-ended allocation, refer to the chip manual, in addition, it is not possible to determine the physical location relationship between the pad in the internal die based on the physical location of Figure 1 in the pin introduction in the Altera FPGA. You need to use View> pad view to view the physical location relationship.

 

Further description of the pin in Altera FPGA