GDT,LDT,GDTR,LDTR detailed, package you understand thoroughly

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First, the introduction

The segment register in protected mode is composed of a 16-bit selector and a 64-bit segment Descriptor Register

Segment Descriptor Register: Bucket Descriptor

Selector: The index of the bucket descriptor

Segment Register

PS: Each segment register in the original real mode as a segment selector in protected mode, 80486 with 6 (i.e. Cs,ss,ds,es,fs,gs) 80-bit segment registers. The segment represented by the selector CS is still a code snippet, and the segment represented by the selector SS is still a stack segment.

Second, detailed

First explain the concept

(1) Global Descriptor List GDT (Global descriptor Table) in the whole system, there is only one (one processor for a GDT) in the overall descriptor, the GDT can be placed anywhere in memory, but the CPU must know the entrance of the GDT, That is, where the base site is located, the Intel Designer door provides a register GDTR to hold the entry address of the GDT, the programmer sets the GDT to a location in memory, and the LGDT command can load the GDT's entry address into this register, The CPU accesses the GDT based on the contents of this register as the entrance to the GDT. The GDTR store is the base address of the GDT in memory and its table length bounds.

Base site Specifies the address of the GDT table in byte 0 in the linear address space, and the table length indicates the byte length value of the GDT table. The instructions LGDT and SGDT respectively use facilitates and save the contents of the GDTR register. The base address is set to 0 by default and the length value is set to 0xFFFF after the machine has just been added or the processor is reset. A new value must be loaded for GDTR during the initialization of the protected mode.

GDTR

(2) Segment selector (Selector) access to the global descriptor by GDTR is done through the segment selector (the segment register in real mode). Segment selector is a 16-bit register (same as segment register in real mode)

Segment Selection Sub

Segment selectors include three parts: Descriptor index, TI, request privilege level (RPL). His index (Descriptor indexes) section represents the position of the desired segment descriptor at the descriptor list, and the corresponding descriptor can be found by this location based on the descriptor map base stored in the GDTR. Then use the segment base in the descriptor table with a logical address (Sel:offset) OFFSET can be converted to a linear address, the segment selection of the TI value is only one 0 or 1, 0 means that the selection is in the GDT selection, 1 means that the selection is in the LDT selection. The request privilege level (RPL) represents the privileged level of the selected child, with a total of 4 privileged levels (level 0, 1, 2, 3).

Description of the privilege level: each segment in a task has a specific level. Whenever a program attempts to access a segment, it compares the privilege level owned by the program with the privilege level to be accessed to determine whether the segment can be accessed. The system convention is that the CPU can only access segments of the same privileged level or lower privileged level.

For example, give the logical address: 21h:12345678h converted to a linear address

A. Select Sub sel=21h=0000000000100 0 01b He means: Select sub-index=4 that is 100b to select the 4th descriptor in the GDT; the ti=0 represents the selection of the GDT, and the 01b on the left represents the privileged level rpl=1

B. offset=12345678h if the segment base (base) described in the fourth descriptor of the GDT is 11111111h, then the linear address =11111111h+12345678h=23456789h

(3) Local Descriptor Table LDT (local descriptor table) Local descriptor tables can have a number of sheets, each task can have one. We can understand that GDT and LDT:GDT are first class descriptor tables, and the LDT is a level two descriptor table.

Local Descriptor descriptor of LDT

The LDT and GDT are essentially the same, but the LDT is nested within the GDT. LDTR records the starting position of the local descriptor, unlike GDTR, the LDTR content is a segment selector. Since the LDT itself is also a piece of memory, is also a segment, so it also has a descriptor to describe it, the descriptor is stored in the GDT, corresponding to the descriptor will also have a selector, LDTR loaded is such a selector. LDTR can be changed at any time in the program by using the LLDT directive. For example, if the load is selector 2 then LDTR points to the table LDT2. For example, if we want to select the address 12345678h of the segment described in the third Descriptor in table LDT2.

1. First you need to load the LDTR to point it to LDT2 using instructions Lldt load Select2 to LDTR

2. The index=3 representative of the SEL selects the third descriptor when the logical address (sel:offset) is accessed, and the Ti=1 represents the selection in the LDT, when ldtr points to LDT2, so it is selected in LDT2, at which time the SEL value is 1Ch (binary 11 1 00b). offset=12345678h. Logical address is 1c:12345678h

3. A descriptor is selected by the SEL, and a linear address can be obtained by adding offset from the base address (base) in the descriptor, for example, if the base address is 11111111h, then the linear =11111111h+12345678h=23456789h

4. At this point, if you want to access the third descriptor in LDT1, just use the Lldt instruction will select sub-selector 1 load and then execute 2, 32 steps (because at this point LDTR also point to LDT1)

Since each process has its own set of program segments, data segments, stack segments, with a local descriptor, the program segments, data segments, and stack segments of each process can be encapsulated together, and the segments of different processes can be accessed as long as the LDTR is changed.

When the task is switched on, the processor automatically loads the segment selection Fu descriptor of the new task Ldt into the LDTR. After the machine power-on or processor reset, the segment selector and base address are set to 0 by default, and the segment length is set to 0xFFFF.

Iii. examples (very useful for understanding)

1: Visit GDT

Segment Descriptor in GDT

When ti=0 represents the segment descriptor in the GDT, as shown in:

① gets the GDT base address from the GDTR register first.

② then in the GDT the high 13-bit position index of the segment selector is worth the segment descriptor.

The ③ segment describes the character contains the base address of the segment, the limit length, priority, and other properties, which gives the beginning of the segment (base), and then with the base address plus offset addresses yyyyyyyy to get the last linear address.

2: Access to the LDT

Segment descriptor in the LDT

When Ti=1 represents the segment descriptor in the LDT, as shown in:

① still obtains the GDT base address from the GDTR register first.

② Gets the position index (LDTR high 13-bit) of the section of the LDT from the LDTR register.

③ Gets the LDT segment descriptor in the GDT with this position index and obtains the base address of the LDT section.

④ using the segment selector high 13-bit position index value to get the segment descriptor from the LDT segment.

The ⑤ segment describes the character contains the base address of the segment, the limit length, priority, and other properties, which gives the beginning of the segment (base), and then with the base address plus offset addresses yyyyyyyy to get the last linear address.

Extended

Besides GDTR and LDTR, there are IDTR and TR

(1) Interrupt Descriptor Descriptor Register IDTR

Similar to the role of GDTR, the IDTR register is used to hold the 32-bit linear base address and 16-bit table length values of IDT for interrupt descriptor tables. The instructions Lidt and Sidt respectively use facilitates and save the contents of the IDTR register. The base address is set to 0 by default and the length value is set to 0xFFFF after the machine has just been added or the processor is reset.

(2) Task Register TR

The TR is used to address a particular task State segment (Task Segment,tss). The TSS contains important information about the current execution of the task.

The TR register is used to hold 16-bit segment selectors, 32-bit base addresses, 16-bit segment lengths, and descriptor attribute values for the TSS segment of the current task. It references a type of TSS descriptor in the GDT table. The instruction ltr and STR are respectively facilitates and the segment selector portion of the TR register is saved. The Subgrade address, segment limit length, and descriptor attributes in the TSS descriptor are automatically loaded into the task register when the selection Fugazai into the task register using the LTR directive. When performing a task switch, the processor automatically loads the segment selection Fu descriptor for the TSS of the new task into the task Register tr.

GDT,LDT,GDTR,LDTR detailed, package you understand thoroughly (turn)