Getting started with "make"
Author: suminder S. Ahuja
Translation: AI
Body:
Overview
Makefile Introduction
Makefile Composition
Note
Explicit rules
Make execution
Benefits of using make
Define Variables
Reference replacement and calculation variable name
Recursive extension and simple extension variable
Add text to a variable
Automatic Variable
Variable values for specific targets and modes
Implicit rules
Instructions
"Define" indication
"Include" indication
"Override" indication
Command echo
Pseudo target
Use wildcards in file names
Command Errors
Parallel Execution
Use make to update an archive file
Conclusion
Additional reference
About the author
Overview
Make is a tool in UNIX that is used to automatically create and optimize programs. It is especially useful when the programs you develop consist of many components or source files.
A descriptor file named makefile clarifies the relationship between source files and provides commands for Updating each file. when one of the source files is changed, make calls makefile to automatically recreate the program. because only the files affected by the changes are recompiled, the compilation time is reduced. it also helps reduce the possibility of human error when creating these entries using command lines.
In addition to compilation, make is also an effective tool for installing programs and changing system configurations.
Makefile Introduction
Create a configuration file named makefile for each project. after each source program is modified, make calls makefile to execute necessary re-compilation. make searches for the description file in the current working directory in the following order:
Makefile
Makefile
By default, the simple make command only creates the first target in the file. The other common usage of the make command is as follows.
Make prog1 create the target "prog1"
Make-F mymakefile uses "mymakefile" as the configuration file to create the first target in the source file
Make-F mymakefile prog1 uses "mymakefile" as the configuration file to establish the target "prog1"
Makefile Composition
Makefile contains five main parts: Comments, explicit rules, variable definitions, implicit rules, and instructions.
Note
In makefile, the content starting from '#' to the end of the line is a comment. A comment can be extended to multiple rows, as long as one ('/') is added at the end of the row, but this backslash cannot be escaped by another backslash. the comment can be placed in any position in a row. The content before '#' does not belong to the comment. the default/bin/sh shell allows command line comments, but does not allow comments when defining instructions.
Explicit rules
Makefile consists of 'rules. the Rules describe when and how to recreate certain files. These files may be the targets of other specific files. A rule consists of one or more targets, zero or multiple prerequisites, and zero or multiple commands ).
Target...: prerequisites
Command
...
...
The target is the common name of the domain created by make; for example, an executable file or a target file. the target can also be the name of the action to be executed, for example, clean (see Pseudo-target ). once any prerequisite changes, the target will be created. if the target exists and is newer than its prerequisite, the target is regarded as "latest.
A prerequisite is one or more files used as input for creating a target. The prerequisite is to define the dependency attributes of some targets on some source files.
The command is in a prerequisite rule. it is the action taken by make to create or update a target when any prerequisite changes. A rule can contain multiple commands. each Command executed in the rule is interpreted and executed by shell. by default, make uses/bin/sh shell. macro shell = bin/sh will overwrite the default shell.
Make execution
Make follows the "dependency rule" concept. Make reads the makefile in the current directory, starting from processing the first target. make searches for the dependencies (Prerequisites) of each target to see if they are listed as the target.
Make traverses the entire recursive chain along the dependency chain until a target without any precondition is found, or its prerequisite has no rules. once the end of the dependency chain is reached, make returns recursion and executes the commands in each target rule in the returned process. make adopts the same pattern for all the prerequisites with rules.
Once all the prerequisite rules are completed, make returns the first target. if the target does not exist, or the target is generated earlier than the prerequisite, make runs the command to generate the target, as shown in the following example of a makefile (example 1.0 ).
# Examples 1.0
# Linking object files
Prog1: Main. O file1.o/
File2.o display. o
CC-O prog1 main. O file1.o/
File2.o display. o
# Compiling source files
Main. O: Main. c mydefs. h
CC-C main. c
File1.o: file1.c mydefs. h
CC-C file1.c
File2.o: file2.c command. h
CC-C file2.c
Display. O: Display. C command. h
CC-C display. c
# Compiling source files
.. Phony: clean
Clean:
Rm prog1 *. o
# End of makefile
NOTE: Refer to command echo.
In the previous example, we have assigned values to the variable objs.
Objs = Main. O file1.o file2.o display. o
Once the variable is defined, its value can be extracted using $ (variable) or $ {Variable. however, if parentheses are omitted, only the first character of the variable name is used. therefore:
• $ (Objs) gets the value of the variable objs.
• $ Objs get the variable O value (if there is variable O ).
Make can flexibly use undefined variables; in this case, the value returns an empty string. Before setting a variable, make can use the shortcut character '? = 'Check whether it has been set. The following example checks whether Foo has been set:
Foo? = Bar
If not, make will assign a value to it.
Reference replacement and calculation variable name
There are also two advanced features of referenced variables: Reference replacement and variable name calculation.
• Reference replacement
Replace the value of the variable with the value you specified. the format is as follows: '$ (VaR: x = y)', which means to get the value of the variable VAR and replace X at the end of each word in the variable value with Y, and replace the result string. in the following example, the bar is set to. c B. c. c:
Foo: = A. o B. O C. O
Bar: = $ (FOO:. O =. c)
• Variable name Calculation
Another variable can be referenced within the variable name. This is called the variable name.
Example:
A = B
B = C
X: =$ ($ ())
In this example, the X value is 'C '. $ (a) expands to 'B', so $ (a) is $ (B), and $ (B) expands to 'C '.
Recursive extension and simple extension variable
There are two methods for obtaining values for variables: recursive extension variables and simple extension variables.
Recursive extension variable simple extension variable
Use '=' for row assignment or use "Define" to indicate row ': =' for assignment.
The specified value is assembled verbatim. The variable is scanned once at definition to obtain its value.
Whenever a variable is replaced, the reference to other variables is expanded. References to other variables are not included; values are included.
Example:
Foo = $ (bar)
Bar = $ (Yep)
Yep = Hello
Command:
ALL:; echo $ (FOO)
The 'Hello'. $ (FOO) is expanded to $ (bar), $ (bar) is expanded to $ (Yep), and finally to 'Hello'. Example:
A: = foo
B: = $ (a) bar
A: = Hello
It is equivalent:
B: = Foo bar
A: = Hello
The execution is purposeful, but it causes the make operation to be slow, because the reference in this definition is executed every time the variable is extended. It is easier to predict the compilation of complicated makefiles.
Add more text to the variable
We often need to add more text to an existing variable. the shortcut operator '+ =' provides this flexibility. in the following example, get the objs value and add the text file3.o to the value:
Objs + = file3.o
In this way, we can set objs to main. O file1.o file2.o display. O file3.o:
Objs = Main. O file1.o file2.o display. o
Objs + = file3.o
Automatic Variable
Based on the Goals and prerequisites of the rules, the values of these variables are different in each executed rule. in Example 1.2 of the following implicit rule, '$ @' is used for the target file name and '$ +' is used for the source file name.
Common automatic variables include the following.
$ @
Name of the Rule target file
$ %
Target member name. The target is an archive member.
$ <
First prerequisite name
$?
Names of all prerequisites for the comparison
$ ^
All prerequisite names separated by space characters
$ +
Similar to '$ ^', but repeated prerequisites are listed multiple times in the order they are listed in makefile.
Variable values for specific targets and modes
• Specific target variable value
Depending on the target created by make, this function can assign different values to the same variable. The value is available locally in the context of the target Command Script. The format is as follows:
Target...: Variable-assignment
The following statement sets cflags to-G in the Command Script of prog1 and its prerequisites:
Prog1: cflags =-G
Prog1: Main. O file1.o file2.o display. o
• Specific mode variable value
This feature allows you to define a variable for any target that matches this special pattern. the format is '% '. in the following example, for all matching modes %. O target assigned to cflags value-O:
%. O: cflags =-o
(For more information, see additional references .)
Implicit rules
Implicit rules tell make how to use the conventional method, so that they do not have to be specified in detail each time they are used. one of the implicit rules is to use the CC-C command to update the file '. o'', the source file is the corresponding '. c' file. with implicit rules, makefile in the previous example can be written in the following format (example 1.2 ).
# Examples 1.2
#1
# Defining the Compiler
Cc = gcc
#2
# Defining the object (objs) Variable
Objs = Main. O file1.o file2.o display. o
#3
# Linking object files
Prog1: $ (objs)
$ (CC)-o $ @ $ +
Echo prog1: make complete
#4
# Tell make how to build. O from. c files
%. O: %. c
$ (CC)-C $ +
#5
# Compiling source files.
Main. O: mydefs. h
File1.o: mydefs. h
File2.o: Command. h
Display. O: Command. h
#6
# Removing the executable and object files
.. Phony: clean
Clean:
Rm prog1 $ (objs)
Echo clean: make complete
# End of makefile
Note:
1. compiler variables provide the flexibility to use different compilers for the same makefile.
2. The variable objs is defined as the entire target file.
3. '$ @' the automatic variable indicates the target, and '$ +' indicates the prerequisite for all variables to be separated by spaces.
4. The pattern rule tells make how to convert *. c files to *. O files.
5. Make has a built-in mode to convert *. H files to dependent *. O files.
6. Make deletes the prog1 and all object files in the existing Directory (see Pseudo targets ).
Commands created using implicit rules use predefined variables. These variables are classified into two types: Program names (such as CC) the other type is specific variables (such as cflags) corresponding to these programs ).
The following are the variables used as program names in some built-in rules.
Ar
Archive file maintenance program. The default value is ar.
As
The Program for compilation. The default value is.
CC
Compile the C program. The default value is CC.
Cxx
Compile the C ++ program. The default value is g ++.
Rm
File Deletion command. The default value is RM-f.
The values of the following variables are program-attached parameters.
Arflags
Indicates the archive maintenance program. The default value is RV.
Asflags
Additional identifier for the assembler
Cflags
Additional flag for the C Compiler
Cxxflags
Additional flag for the c ++ Compiler
Instructions
"Define" indication
Define indicates to assign a value to the variable. Define indicates that the variable name is in the same line. The value of the variable is in the next line. The endef in the last line indicates that define ends. Define is similar to '=', for example:
Define two-Lines
Echo foo
Echo $ (bar)
Endef
The difference between a normal value assignment and a define indicator is that a normal value assignment cannot contain line breaks, while a line break in a define value is a part of a variable value.
The functions of the preceding example are equivalent:
Two-lines = echo Foo; echo $ (bar)
The two commands separated by semicolons act like the two shell commands respectively. However, note that in the two lines, make will call two shells and run an independent sub-shell for each line.
"Include" indication
Instruct include to tell make to stop reading the current makefile and then read each listed file. After reading the file, make will re-read the makefile where it appears in the instruction. The format is as follows:
Include filenames...
Filenames can contain the shell file name mode.
For example, if you have three '. MK 'file, 'x. MK ', 'Y. MK ', and 'z. MK ', and $ (bar) is expanded to bish bash, then the following expression:
Include Foo *. mk $ (bar)
It is equivalent:
Include Foo X. mk Y. mk Z. mk bish bash
One use of the include indicator is to assign a public variable definition set to the program processed by the respective "makefile" file.
"Override" indication
Override indicates that you can set variables that have been set with command parameters in makefile. The format is as follows:
Override variable = Value
Add text to the variable defined in the command line with the following code:
Override variable + = more text
This indicator was invented to change or increase the value specified by the user in the command line. for example, assume that you always want the C compiler to use the-G switch, but you do not want users to specify other switches using command parameters as usual. you can use override to indicate:
Override cflags + =-G
Command echo
Make displays the progress of makefile before a line is executed, which is called Echo. commands starting with '@' can also be used to indicate the progress of makefile without echo. as shown below:
Echo prog1: make complete
With the-n flag added, make only displays commands but does not actually execute them. in this case, the command is displayed even if it starts. to prevent all Echo, you can use the-s flag. the output is as if every command starts.
Pseudo target
A pseudo-target is an action caused by an explicit request rather than a file name. commands in the pseudo-target do not create any targets, but the command must be executed every time the target is rebuilt. For example:
Clean:
Rm prog1 *. o
When the command is explicitly called as follows, prog1 and all target files will be deleted:
Make clean
Because RM is not creating a file named clean, it may not exist at all. however, if someone creates a file named clean in this directory, the pseudo-target will stop working. when there are no prerequisites for file clean, it is regarded as the latest update and its command will not be executed.
To avoid this problem, the target is defined as. Phony. In the following example, make clean runs the command, regardless of whether the file named clean is true:
. Phony: clean
Clean:
Rm prog1 *. o
Use wildcards in file names
A single file name can use wildcards to indicate multiple files. Make is used as a prerequisite for the target. Wildcards '*', '? Are Used in commands and variables '*','? ', And' [...] '. wildcard can be used in Rule commands. These commands are expanded by shell. For example, this is the rule for deleting all target files:
Clean:
RM *. o
When you define a variable, the wildcard is not expanded. That is, if you write:
Objects = *. o
The variable object value is a real string '*. o '.
Command Errors
After the command is executed, make checks the exit status to verify that it has been successfully completed, and sends the next command to the new shell. if an error is returned, make will discard the current rule and may discard all rules. to ignore errors in the command line, add the '-' sign at the beginning of the line (after the initial tab ). '-' is discarded before the command is passed to the shell for execution. the following example continues running even if RM cannot delete the file ,:
Clean:
-Rm-f *. o
Similar features can also be implemented by adding the-I parameter after make; errors of all commands in all rules are ignored.
Parallel Execution
By default, make runs only one command at a time and waits until the execution of the previous command ends. make uses the '-J' option to execute multiple commands at the same time. an integer with the '-J' option suffix specifies the number of jobs that can be run at a time.
Use make to update an archive file
Archive files called members are generally used as links to sub-libraries. They are maintained by the program ar. The format is as follows:
Archive (member)
An independent file member in make can be used as a target or a prerequisite. In the following example, create a member Foo. O in archive sublib by copying the file Foo. O:
Sublib (FOO. O): Foo. o
Ar Cr sublib Foo. o
Conclusion
This document is a getting started tutorial on using makefile. It covers all the knowledge. Make also has many features that can be found in the following reference. Use your new makefile to try it.
More references
1. GNU make, a program used to guide recompilation
2. Sun's make official reference page (Sun official reference page on make)
About the author
Suminder Singh Ahuja is a software engineer with four years of experience working in intensive transaction technologies and databases, including TPF, IBM 370/390, Vm/CMS, and UNIX. he has been working in Galileo for three years and is in charge of airline ticket booking solutions. contact him suminder: suminder@rediffmail.com
July 2002
