Global mainstream 8-bit MCU chip detailed anatomy No.2: Infineon XC866-Full text

Reading guidance The XC866 is the first generation of the new 8-bit microcontroller family (XC800), with integrated high-performance 8051-core, on-chip flash, and powerful peripheral sets. In addition, the XC800 family of internal integrated on-chip oscillators and embedded voltage regulators (EVR) that support single-supply 3.3V or 5.0V further enhance product performance and effectively save system costs.

Key Words:XC8668-bit MCU Infineon

　　Previous series articles recommended:

Global mainstream 8-bit MCU chip anatomy first: Freescale MC9S08AC60

　　Brief introduction

The XC866 is the first generation of the new 8-bit microcontroller family (XC800), with integrated high-performance 8051-core, on-chip flash, and powerful peripheral sets. In addition, the XC800 family of internal integrated on-chip oscillators and embedded voltage regulators (EVR) that support single-supply 3.3V or 5.0V further enhance product performance and effectively save system costs. In addition to offering on-chip flash products, XC866 also offers the same series of compatible ROM products, providing a further cost-saving space for mass production.

Single chip microcomputer structure diagram

Pin diagram

Multi-Function Pin Example

-p0.0 Pin 12

TCK_0 JTAG Clock Input

t12hr_1 CCU6 Timer 12 hardware Run input

Cc61_1 Capture/Compare Channel 1 input/output

Clkout Clock Output

Rxdo_1 UART Transmit Data output

-p0.1 Pin 14

TDI_0 JTAG Serial Data input

t13hr_1 CCU6 Timer 13 hardware Run input

Rxd_1 UART receiving data input

Cout61_1 Capture/Compare Channel 1 output

Exf2_1 Timer 2 external flag output

　　Module analysis

　　Memory structure

-8k Start (boot) ROM address: c00h-e000h

-256-byte on-chip ram,0~7fh using direct addressing, 80~FFH use

(1) Register indirect addressing

-128 bytes SFR address 80~FFH, using direct addressing

-512 bytes Xram address f000~f200, accessed using MOVX. When using R0,R1 as the address register, the high address of its Xram address is defined by the value in the Register XADDRH.

-8k/16k program memory, starting address 0000

-Special EO register operation that allows switching dptr as well as to program ROM

-Write operation (instruction: MOVC @ (dptr++), A) implement software update

(2) Basic port structure diagram

(3) Port-related registers

-Px_pudsel pull/drop-down selection register

-px_puden Pull/pull-down enable register

-px_od Open-Drain control register

-Px_dir Direction Register (P2 port only as input)

-Px_altsel0 second function selection Register 0

-px_altsel1 Second function Selection Register 1

-Px_data Port Data register

where PX x is the port number, the register is 8 bits, each bit corresponds to a pin

　　I²c Bus and SPI bus

The I²c bus and SPI bus belong to the serial interface of "bit synchronization", but there are some different points:

The data signal of the NN-i²c bus needs to be: Start, stop and ACK signal, request the other party to answer

I²c Bus Circuit link

SPI bus: Two serial data cable, one clock line. The data line is divided into output and input. For multiple parts of the chip, you also need to select CS.

SPI Bus Structure

　　SSC in XC866

The XC866 has a high-speed synchronous serial channel SSC, which can be compatible with SPI, or compatible with 8051 serial port mode 0;

-Baud rate can be programmed independently: it has a dedicated, 16-bit baud rate generator with heavy load function;

-The data width is specified as 2~8 bit "character";

-The LSB can be sent first (compatible with 8051 serial port mode 0) or the MSB (compatible with SPI) can be sent first;

-The data can be shifted on the rising or falling edge of the clock;

-can generate shift clock or receive shift clock;

-Different names: MOSI=MTSR, Miso=mrst;

SSC Composition block Diagram

　　Digital-to-analog converters (DA)

Working principle

Da Converter Chip

The main components of the DA converters are resistor networks and corresponding analog switch arrays.

The analog output is usually the current output, the op amp in the diagram converts the current output into a voltage output, connected by the feedback resistor designed by the manufacturer, and the output voltage and the reference voltage meet the following relationship:

Vout=-Vref X (Data/(2n-1))

where n is the number of digits, data for the input of the digital number of the chip with a data latch, self-provided reference voltage. A wide range of chip models, common DAC0832 and so on.

　　AD Converter

-Successive approximation

-8-bit or 10-bit accuracy, 8-way analog channel

-4 Independent result registers

-One-time conversion and automatic scanning function

-Sample clock programmable, clock divider programmable

-Integrated sample-and-hold circuitry

-Data compression filtering

-Flexible interrupt generation mode, interrupt service node configurable

-Can turn off the ADC module to reduce power consumption

XC866 AD Converter Block diagram

Initial resolution of AD conversion

AD Converter Initialization Program:

-sfr_page (_ad0, NOSST); Switch to page 0

-adc_globctr = 0x70; f32,8 bit width

-adc_prar = 0x94; Set arbitration method and priority

-Sfr_page (_ad1, NOSST); Switch to Page 1

-adc_qmr0 = 0x00; ADC mode, no external triggering

-ADC_CRMR1 = 0x01; ADC mode, open Request source

-sfr_page (_ad0, NOSST); Switch to page 0

-adc_globctr |= 0x80; Opening the simulation section

-XC866 ADC uses 7 pages of SFR, each of which occupies address cah~cfh and d2h,d3h. With different content on the page, use D1H as the paging register to make sure that the page is used. Globctr and Prar on 0 pages, QMR0 and CRMR1 on 6 pages.

　　Programmable counter array PCA and capture comparison unit CCU

Enhanced Timer/Counter module, or multiple module combinations, called PCA/CCU

-Timer clock selectable: Another timer overflow or fixed divider output

-Selectable capture/compare/reload/PWM output and more

-Multiple capture/compare/reload data registers make up multiple PWM outputs

-Capture/overflow/match can generate interrupts

-Separate reload register to set PWM cycle

　　Capture comparison unit for XC866 CCU6

The Capture/Compare Unit 6 (CCU6) has two independent timers (T12,T13) that can be used to generate pulse-width modulated (PWM) signals, especially for applications that control AC motors. The CCU6 also supports some dedicated control modes for block switching and multiphase motors.

The 3 channels of the timer T12 can operate in capture and/or comparison mode. Timer T13 only works in comparison mode.

The output sequence produced by the multichannel control unit can be modulated by T12 and/or T13. The modulation source can be selected and used in combination.

　　Timer T12,T13 Features:

-Timer T12 Features:

1.3-way capture/compare channel, each can be used as a capture or compare channel

2. Support the generation of three-phase PWM (6-way output, each signal corresponding to the upper or lower bridge arm switch)

3.16-bit accuracy, max count frequency = peripheral clock frequency

4. Single channel dead Time control, avoid power level short circuit

5. Sync Refresh t12/t13 Register

6. Produces intermediate alignment and edge-aligned PWM

-Timer T13 Features:

1. Single comparison channel, single output

2.16-bit accuracy, max count frequency = peripheral clock frequency

3. Can synchronize with T12

　　A brief introduction to three-Soma PWM generation

Three-phase different pulse width values need to be written to the ccu6i mapping register in real time CCU6ISR

The u,v,w three-phase output is paired with the output via the ccu6i and cout6i pins, opposite polarity

Various settings: Clock selection, Prescaler selection, dead time, Output pin configuration, and multiple mode selection, here's a little bit.

　　Three-Soma SPWM signal principle

Triangular waves are called "carriers", and sine waves are called "modulated waves". A,b,c Three phase phase difference 120 degrees, their SPWM waveform parameter table is actually the same, but also the difference of 120 degrees.

The SPWM waveform parameter table is actually the corresponding pulse width in each triangle wave period.

　　Three-phase motor/brushless motor Control Example

Single-chip microcomputer CCU6 output u+/u-; V+/v-and w+/w-are driven to connect to the IGBT.

Real-time change of cycle and pulse width, can achieve the purpose of frequency conversion, and adjust the output power, thereby controlling the motor speed.

　　The engineers ' questions and answers about XC866 's use:

(1) What kind of IDE should XC866 choose?

A: "Miniwigger+keil V3 cracked version

Keil for C51 V8

Infineon Dave v2.1

Infineon Memtool v4.01.05

Fload Downloader "

(2) Want to use Proteus simulation of Infineon's XC866, but the component library does not, how to do?

A: "Because Proteus's component library does not have Infineon's MCU, its own production is more difficult, if it is other commonly used devices, find a similar replacement." Can use Miniwager, is Infineon's own emulator, also can use Nanjing Wei Fu's multi-infineon simulator. ”

(3) Sclk clock problem in Infineon XC866

Q: The SSC has been set up in Dave, but when the program is programmed in Keil, it is found that the SCLK is always 0,xc866 not a SSC setting to produce a clock signal?

A: "comes with the SPI peripheral, when the data is sent to the clock output." ”

(4) XC866 MBC level OCDs mode Help

q:xc866 Development Board. Using Ulink through the OCDs interface debugging, the book says: if (mbc,tms,p0.0) = (0,1,1), will go into the OCDS mode for program code debugging. First initialize the OCDs, then jump to the program memory address 0000H, execute flash or ROM memory in the user code, start debugging. In OCDs mode, the low 64 bytes (address 00h-3fh) of the internal data memory can be selected to be mapped to 64 bytes of monitoring RAM or internal data ram.

Why use Ulink debugging, MBC pin is always high, ah, and the book said not the same AH. Use a multimeter to see, is it the MBC instantaneous low level after entering the OCDs mode, and then set high.

When writing a program with Xc800_fload, the MBC PIN must be specifically given to the ground, or it cannot be burned.

A1: "(mbc,tms,p0.0) = (0,1,1) refers to the chip reset the level of these feet, xc866 after the reset will automatically detect the level of these three feet determine whether the chip into the download mode, Jtag mode, or run the program. For your question.

1. OCDs Mode: Your understanding may be right, because MBC, TMS, P0.0 will connect to Ulink, so I guess the actual process is this, Ulink first will MBC, TMS, P0.0 set to 0,1,1. Then reset the chip (Ulink pull down reset), release the Reset chip, this time the chip into the OCDs mode.

2. If MBC = 0. TMS = 0, the chip reset after entering the BSL mode, serial download (through Fload) "

A2: Also said, in the Ulink connection, Keil software interface Click the Debug button, Ulink first let the chip reset, and then set the MBC, TMS, P0.0 for (0,1,1) let the chip into the OCDs mode. After entering the mode, the MBC, TMS, P0.0 settings are restored to normal mode. In this case, for example, in the breakpoint debugging, the person presses the reset key, the chip can enter the normal operation mode, the program is running normally, instead of entering OCDs mode.

and Fload mode, from the circuit, MBC can only be ulink OCDs signal control, so need to artificially add low level, and after burning the program, the program can not run.

　　XC86 Related information download :

1. XC866-based stepper motor valve control system

2. Sine wave control of PWM DC brushless motor based on XC866

3, XC866 series microcontroller design of electric bicycle controller technology

Global mainstream 8-bit MCU chip detailed anatomy No.2: Infineon XC866-Full text