Go Combined simulation of Quartus II and Modelsim (detail)

First recommend a post http://www.cnblogs.com/emouse/archive/2012/07/08/2581223.html

First, according to the previous article, set up a testbench template;

The first time you use modelsim+quartus, you need to set Modelsim path in Quartus, Quartus->tools->general->eda tool options, On the right, select the installation path for Modelsim, such as:

Then set the Emulation tool in Quartus->setting->simulation (select Modelsim), Output the Netlist language (select VHDL or Verilog), and add testbench below:

To edit test settings This step need to explain, where test bench name can be determined by itself, the following two of the content according to the test bench file.

For example, the test bench I wrote with Verilog is as follows:

Then I have the following two names for COUNTER_TB and Counter, respectively:

If it is written in VHDL test bench, such as

So the following two of our content is adc_vhd_tst and I1, as

once this is set up, the RTL simulation and gate (timing) simulation can be performed directly from the Quartus, (tick represents the use of timing simulation); Why do you want to set this up ? See Http://www.uio.no/studier/emner/matnat/fys/FYS4220/h12/documentation/quartus_modelsim_setup.pdf If you don't set this up, RTL simulations can be performed, but gate-level (timing) simulations are not possible, and Failed to find INSTANCE errors are reported when gate-level (timing) simulations occur .

To do the last one can write programs, then compile, then run RTL simulation, this time Modelsim will start themselves, and then compile themselves, and then in the work library there will be two units, of which one is testbench generated, we simulate the words with this. Then add the waveform or something to simulate it.

To run the timing simulation, click the Gate-level Simulation button on the quartus.

then the most critical question came , if we modify the VHDL program or testbench, how to update in the Modelsim , I found a lot of tutorials on the Internet, find only to do the last step on the end, Update in Modelsim only to turn off Modelsim, RTL simulation in Quartus, obviously this is very troublesome, until I see this article http://www.cnblogs.com/emouse/archive/ 2012/07/08/2581223.html, this way. The 7th step in the end is completely free to do, and I'll talk about my approach.

When running RTL simulation, Modelsim will start itself, and start compiling, this is when in fact it has a command is entered, you can press the UP arrow in Transcripe, you will find a do ****.do command, You can find this do file in the Simlation folder, If you do RTL simulation, there will be ****rtl****.do files, and also, if the gate-level simulation, there are *******gate****.do files, Please note the distinction. When you modify the program to want to update in the Modelsim, the direct knocking on the Do *****.do command is OK, but each time the command will be re-compiling the library file, greatly wasting time, so you can find this file, open, the above part of the compilation of the library file instructions to comment out Such as:

This time the Do command is executed, the execution is completed in a few seconds, and the Modelsim is updated.

Of course Modelsim can also not test bench simulation, you can hit the force command to generate waveforms, specifically find Information Bar.

In test bench, the input signal is initialized, otherwise it will show ' X ' any state, and it cannot be initialized in one process, or it will be rendered ' x ' in other process, preferably using a previous initialization.

As if the RTL simulation modified the VHLD file does not need to compile, directly using the DO command can update the simulation results, gate-level simulation needs to compile, and then use the Do command to update

Go Combined simulation of Quartus II and Modelsim (detail)