Go into the Cache of the CPU

After reading the previous article, you may be wondering why the results of the program will be so, now, let's go into the world of CPUs.

In the SMP (symmetric multiprocessor) era, multiple CPUs work together to further enhance the computing power, so how does the CPU coordinate memory access?

     +--------------+                   +--------------+          |                   CPU0 |     |          CPU1 |                       +--------------+                   +--------------+             ^         |                ^         |         |                       |         |                |         |         V |     V |     +--------+                  | +--------+ |<--> |                  Store | |<--> |           Store |     | |                  Buffer |     | |           Buffer |     |     +--------+                  |         +--------+           |                       |         |                |         |         V |     V +--------------+ +--------------+ |                   Cache |     |          Cache |                                  +--------------+                   +--------------+                 |                      |  |                                | +------------+                     +------------+                       |                     Invalidate | |               Invalidate |   |                     Queue |   |        Queue |            +------------+                     +------------+              |                               Interconnect |                  +----------------------------------+                              |       +-----------------------+                  |                  Memory | +-----------------------+

is a modern CPU generally adopted architecture, because the CPU's computing power is much faster than memory access speed, so that memory access becomes the process of instruction execution relatively slow, so in the CPU unit and
There will also be multi-level cache between main memory, often called L1, L2, L3, and the speed of their access is reduced in turn, showing only the existence of a first-level cache. This way, when the CPU accesses the memory, it will first look in its own Cache
Look, see if this memory is already cached, and if it is already in the cache, then the direct access to the cache will complete the function. With the existence of the cache, the CPU operation speed has been greatly improved. Because the cache is more expensive, it is generally small, on my Pentium E5800 computer, the first level of the cache is only 128KBytes.

Caching is made up of cache lines, often called cache line, modern Intel CPUs, generally 64B, usually, the cache is composed of multiple links, my CPU is 4-way Association, here do not want to delve into the multi-way off
How the cache works and is interested in self-access.
When no data is needed in the cache, called Cache miss, this is typically loaded from memory, and the cache is loaded in cache line, and is aligned with the cache line, which is the
Address on the load cache line size of the content into the buffer, which is generally 64 bytes, that is, put the common data in a cache line-aligned memory, such data structure will increase the efficiency of the operation of the reason.
When more than one CPU needs to access the same memory, then the same memory content will appear in the cache of multiple CPUs, the problem is that how to maintain the unity between them is a problem, for example, when the same address is cached at the same time two cache, one to rewrite, Then there must be a means to notify the other cache of the immediate update, so that the other CPU needs to fetch data to get the latest data.
Since the cache has brought these problems, can it be possible to instruct some memory to be cached when accessed, or, more accurately, how to control the shape of the cache when accessing a piece of memory? The answer is yes, we can specify the type of memory. The Mtrrs register allows you to specify the memory type of the physical address range, which is typically stored in these common types:
1. UC (uncacheable), which indicates that the memory cannot be cached.
2. WT (write Through), indicating that the cache and memory are updated when writing.
3. WB (write back), which means that only the cache is updated, and then it's time to write to memory.
4. WC (write combining) This memory will not be deleted by the cache and may be delayed for write operations.
But often, in order to achieve higher efficiency, the use of ordinary memory will generally choose the WB type, that is, memory will be the cache, at this time need a means to ensure consistency between the caches, professional point is cache-coherence.
So how do you know that the cache line in your cache exists in the cache of other CPUs, how to record your own cache line has been modified by itself, need to write back, obviously have some status tags to record these
Things, that's the MESI protocol.
In the MESI protocol, each cache line has 4 states, which can be expressed as 2 bits, respectively:
1. M (Modified)
This line of data is valid, the data is modified, and the data in memory is inconsistent, the data only exists in this cache.
2. E (Exclusive)
This line of data is valid, the data is consistent with the data in memory, and the data exists only in this cache.
3. S (Shared)
This line of data is valid, the data is consistent with the data in memory, and the data may exist in many caches.
4. I (Invalid)
This row of data is invalid.
The truth is being solved in a step-by-step way ...

Go into the Cache of the CPU