[Go] risc-v Architecture Introduction

1. What is the difference between risc-v and other open architectures

If judging only from the two points "free" or "open", the RISC-V architecture is not the first to do a free or open processor architecture.

Before we begin, we'll start by discussing a few representative open architectures to analyze the differences in the RISC-V architecture and why other open architectures have failed to achieve enough success. Civilian hero--openrisc

OpenRISC is an open source RISC processor provided by the Opencores organization based on the GPL protocol.

OpenRISC has the following characteristics:

Use a free, open 32/64-bit RISC architecture.

The processor source code based on this architecture is implemented using Verilog HDL (Hardware description Language).

Has a complete tool chain.

OpenRISC is applied to many companies ' projects. It can be said that OpenRISC is a very broad application of open source processor implementation.

The disadvantage of OpenRISC is that it focuses on implementing an open-source CPU Core rather than defining an open instruction-set architecture, so its architecture is not fully developed, and the instruction set definition does not have the advantages of the RISC-V architecture mentioned in the previous section. More did not rise to the height of the establishment of a dedicated foundation organization. OpenRISC is often considered an open source core rather than a graceful instruction set architecture. In addition, OpenRISC's license is the GPL, which means that all instruction set changes must be open source (and risc-v is not). A--sparc of noble nobility

The SPARC architecture is one of the classic RISC microprocessor architectures, and SPARC was first designed by Sun computers in 1985. SPARC is also one of the registered trademarks of SPARC International Inc., which was established in 1989 to promote SPARC architectures and compatibility testing for the architecture. To promote SPARC's ecosystem, SPARC International is open to standards and licensed to a number of manufacturers, including Texas Instruments, Cypress Semiconductors and Fujitsu. Because the SPARC architecture is also completely open to the outside, there is also a fully open source Leon processor. Moreover, in 1994, Sun also pushed the SPARC V8 architecture into the IEEE Standard (IEEE 1754-1994).

Because the SPARC architecture was originally designed for the server domain, its biggest feature is a large register window, a SPARC-compliant processor that needs to implement a universal register from 72 to 640, each with a width of 64bits and a series of register groups, called the Register window.

The architecture of this register window, since it is possible to switch between different register groups to quickly respond to function calls and returns, can produce very high performance, but this architecture is too expensive for the power area, and is not suitable for PC and embedded domain processors. The SPARC architecture is also not modular, making it impossible for users to crop and select. It is difficult to replace commercial x86 and ARM architectures as a common processor architecture.

The design of such a large server CPU chip is not common companies and individuals can get involved, and the ability to design this large CPU is not necessary to invest a huge cost to challenge x86 's dominance. With the weakening of sun, the SPARC architecture is now largely out of sight. Interested readers please search the Web for articles on their own "good-bye SPARC processor, goodbye Sun" Elite Eugenics--risc-v

This section does not repeat the experience of the birth of Risc-v at the University of Berkeley.

Many universities have introduced a variety of instruction set architectures in research projects because of the many free or open architectures that have emerged over the years in the CPU world. So when I first heard of Risc-v, I thought it was a toy, or a purely academic research project.

Until the author personally read through the RISC-V architecture document, not only for its advanced design concept of the admiration. At the same time, the various advantages of the RISC-V architecture have also been favored by many professionals and many commercial companies have joined in succession. And the 2016 RISC-V Foundation's official launch in the industry has caused a small impact. This makes RISC-V the most revolutionary open processor architecture so far. 2. Simplicity is the design philosophy of the Beauty--risc-v architecture

RISC-V architecture as an instruction set architecture, before introducing the details, let's first understand the philosophy of design. The so-called "philosophy" of design is a kind of strategy, for example, we know the Japanese car design philosophy is the economy of oil, American car design philosophy is the domineering external leakage and so on. What is the design philosophy of the RISC-V architecture? It's "Boulevard to Jane".

One of the most respected design principles of the author is: Simple is the United States, simple means reliable. Countless real-world cases have proved that "simplicity means reliable" truths, whereas more complex machines are more prone to error.

The so-called Road to Jane, in the actual work of IC design, I have seen the most concise design to achieve safe and reliable, has seen the most complicated design long time can not be stable convergence. The most concise design is often the most reliable, and in most of the project practice has been tested again and again.

IC design work is very special, the final output is a chip, and a chip design and manufacturing cycle is very long, can not be as easy as software code upgrade and patching, every time the chip revision to delivery will require a few months of cycle. Not only that, the cost of a single chip manufacturing is expensive, ranging from $ hundreds of thousands of to millions dollars. These characteristics all determine the IC design of the cost of trial and error is very high, so it is very important to effectively reduce the occurrence of errors.

The scale of modern chip design is more and more large, the complexity is more and more high, not to say that the designers blindly evade the use of complex technology, but should be good steel used in the blade, the most complex design used in the most critical scenario, in most cases of choice, as far as possible to choose a concise implementation plan.

The first time I read the RISC-V architecture document, I can't help but admire, Littleshenyang, because the RISC-V architecture in its document is constantly emphasized, its design philosophy is "Boulevard to Jane", trying to define the structure of the hardware to make the implementation of simple enough. Its simplicity is the beauty of philosophy, can be easily seen from several aspects, the following subsections will be discussed. No sickness and light--the length of the architecture

In the processor domain, the current mainstream architecture for x86 and ARM architecture, the author has been involved in the design of the arm architecture of the application processor, so need to read the architecture of ARM documentation, if the reader familiar with it should understand its length. After decades of development, the architecture of modern x86 and arm architectures documents up to hundreds of thousands of pages. Print out can have half table high, can really "prolific".

The reason why the modern x86 and ARM architecture documents are thousands of pages long, and the version is numerous, one of the main reasons is that the development of its architecture has been accompanied by the development of modern processor architecture technology continues to mature.

And as a commercial architecture, in order to be able to maintain the backward compatibility of the architecture, it has to retain many outdated definitions, or in the definition of the new architecture section in order to be able to be the existing part of the technology is very awkward. has become extremely lengthy over time.

Is it almost impossible for a modern, mature architecture to choose to start again and redefine a concise architecture? One of the important reasons is that it is not forward compatible and therefore cannot be accepted by the user. Imagine if we bought a new computer with a new processor or a mobile phone to go home, before all the software will not be able to run and brick, it is certainly unacceptable.

And now the introduction of the RISC-V architecture, then has the advantage of the latter, because the computer architecture after years of development has become more mature technology, over the years in the process of continuous maturation has been the problem of exposure has been studied thoroughly, so the new RISC-V architecture can be circumvented, And there is no backward compatibility of historical baggage, can be said to be free of disease and light.

The current "Risc-v schema document" is divided into the instruction set document (Riscv-spec-v2.2.pdf) and the privileged Schema document (Riscv-privileged-v1.10.pdf). The instruction set document is 145 pages in length, and the privileged schema document is only 91 pages. Engineers who are familiar with the architecture will be able to read them through in just one two days, although the "Risc-v architecture document" is constantly enriching, risc-v is extremely short compared to the x86 architecture document and the ARM architecture document.

Interested readers can download their documents free of charge on the Risc-v Foundation's website (https://riscv.org/specifications/) without registering, as shown in 1.

Figure 1 Schema document flexible on the RISC-V Foundation website--Modular instruction set

The biggest difference between the risc-v architecture and other mature business architectures is that it is a modular architecture. As a result, the RISC-V architecture is not only short and short, but its different parts can also be organized in a modular way, thus attempting to meet a wide variety of applications through a unified set of architectures.

This modularity is not available in the x86 and arm architectures. With ARM architecture as an example, arm's architecture is divided into a, R and M three series, respectively, for application (application operating system), real-time (real-time) and embedded (embedded) Three areas, not compatible with each other.

However, the modular RISC-V architecture enables users to flexibly select different combinations of modules to meet different application scenarios, which can be said to be "young and old". For example, for small-area, low-power embedded scenarios, the user can choose the rv32ic combination of instruction sets, use machine mode only, while high-performance application operating system scenarios can choose such as RV32IMFDC instruction set, Mode (machine mode) and user mode. And their common part can be compatible with each other. Concentration is the essence--the number of instructions

The compact architecture and modular philosophy make the RISC-V architecture a very concise number of instructions. The basic number of RISC-V instructions is only over 40, plus a total of dozens of instructions for the other modular extension instructions. 3. Introduction to the RISC-V instruction set architecture

This chapter provides a brief introduction to the various features of the RISC-V instruction set architecture. Modular subset of Instructions

RISC-V's instruction set is organized in a modular way, with each module represented by an English letter. Risc-v the most basic and only mandatory implementation of the instruction set part is an I-letter representation of the basic integer instruction subset, using the integer instruction subset, you can implement the complete software compiler. Other parts of the instruction subset are optional modules, and representative modules include M/A/F/D/C, as shown in table 1.

Table 1 Modular instruction set for RISC-V

To improve code density, the RISC-V architecture also provides an optional subset of "compression" instructions, denoted by the letter C. The instruction encoding of the compression instruction is 16 bits long, while the length of the normal non-compressed instruction is 32 bits. One particular combination of these modules, "IMAFD", is also known as the "general" combination, denoted by the English letter G. So RV32G said Rv32imafd, rv64g rv64imafd.

To further reduce the area, the RISC-V architecture also provides an "embedded" architecture, denoted by the English letter E. This architecture is primarily used for deep embedded scenarios where very low area and power consumption is pursued. The architecture only needs to support 16 general-purpose integer registers, while non-embedded ordinary architectures need to support 32 general-purpose integer registers.

With the above modular instruction set, different combinations can be selected to meet different applications. For example, the pursuit of small-area low-power embedded scenarios can choose to use the RV32EC architecture, while large 64-bit architecture can choose RV64G.

In addition to the above modules, there are several modules including L, B, P, V, and T. Most of these extensions are still being perfected and defined, and are not finalized, so this article does not discuss this in detail. Configurable Universal Register Groups

The RISC-V architecture supports 32-bit or 64-bit architectures, and the 32-bit architecture is represented by RV32, with a width of 32 bits per universal register, and a 64-bit architecture represented by RV64, with a width of 64 bits per universal register.

The integer universal Register Group of the RISC-V schema, consisting of 32 (I-schemas) or 16 (e-Schema) general-purpose integer registers, where the integer register 0 is reserved as a constant 0, the other 31 (I-schemas), or 15 (e-schemas) are ordinary general-purpose integer registers.

If a floating-point module (f or D) is used, a separate set of floating-point registers is required, containing 32 general-purpose floating-point registers. If only a subset of floating-point instructions for the F module is used, the width of each universal floating-point register is 32 bits, and if a subset of floating-point instructions for the D module is used, the width of each universal floating-point register is 64 bits. Structured instruction encoding

The ability to read general-purpose register groups as soon as possible in the pipeline is often one of the expectations of the processor pipeline design, which can improve processor performance and optimize timing. This seemingly simple principle is difficult to achieve in many existing commercial RISC architectures, because after years of repeated modifications to add new instructions, the Register index position in its instruction code becomes very messy, causing the decoder a burden.

Thanks to the post-advantage and the lessons learned over the years of processor development, RISC-V's instruction set encoding is very structured, and the index of the universal register required by the instruction is placed in a fixed position, shown in 2. Therefore, the instruction decoder (instruction Decoder) can easily decode the register index and then read the Universal Register Group (register file,regfile).

Figure 2 Rv32i-structured instruction encoding format concise memory access instructions

Like all RISC processor architectures, the RISC-V architecture uses dedicated memory read (Load) instructions and memory write (Store) instruction to access memory (memory), which is a common basic strategy for RISC architectures. This strategy makes the hardware design of the processor core simple.

The basic unit of memory access is a byte (byte). The RISC-V memory read and memory write commands support a byte (8-bit), half-word (16-bit), single-character (32-bit) memory read-write operation, and if the 64-bit architecture can also support a double-word (64-bit) memory read-write operation.

The memory access directives of the RISC-V architecture also have the following notable features:

In order to improve the performance of memory read and write, the RISC-V architecture recommends the use of Address-aligned memory read-write operations, but the address is not aligned to the memory operation RISC-V Architecture is also supported, the processor can choose to support the hardware, or choose to use software to support.

Because the current mainstream application is the small-end format (Little-endian), the RISC-V architecture supports only the small-end format. Regarding the small end format and the big-endian format definition and the difference, this article does not do too much to introduce, if does not understand this to the beginner can consult the study independently.

Many RISC processors support address self-increment or auto-subtract mode, and this self-increment or auto-subtract mode increases the processor's ability to access the continuous memory address range, but it also adds to the difficulty of designing the processor. The memory read and memory write instructions for the RISC-V architecture do not support the self-increment mode of the address.

The RISC-V architecture uses a loose memory model (Relaxed memory models), and the loose memory model does not require the order of execution of memory read and write instructions that access different addresses unless masked with explicit memory barrier (Fence) directives.

These choices clearly reflect the RISC-V architecture's attempt to simplify the basic instruction set, simplifying the philosophy of hardware design. The RISC-V architecture is so well defined that it can achieve the flexible effect. For example, for a simple CPU with low power consumption, a very simple hardware circuit can be used to complete the design, while the pursuit of high-performance superscalar processors can improve performance through the complex design of dynamic hardware scheduling capabilities. Efficient branch-Jump instruction

The RISC-V architecture has two unconditional jump commands (unconditional jumps), JAL and JALR instructions. Skip link (jump and link) instruction JAL can be used to make subroutine calls, while the subroutine return address exists in the link register (link register: By a general integer register). The Skip link register (jump and link-register) instruction JALR instruction can be used for subroutine return instructions, which can be returned from the subroutine by using the link register saved by the JAL instruction (jump into the subroutine) for the base address register of the JALR instruction.

The RISC-V architecture has 6 conditional jump commands (Conditional Branch), a conditional jump instruction that uses 2 integer operands as directly as a normal operation instruction, then compares them and jumps if the conditions of the comparison are met. Therefore, this type of instruction will be compared with the jump two operations into one instruction to complete.

As a comparison, many of the other RISC architecture processors need to use two separate instructions. The first instruction uses the comparison instruction first, and the result of the comparison is saved to the State Register; the second instruction uses the jump instruction to determine if the previous instruction was saved in the status register when the comparison result is true. In contrast, this risc-v conditional jump instruction not only reduces the number of instructions, but also the hardware design is simpler.

For low-end CPUs that do not have a hardware branch predictor, the RISC-V architecture explicitly requires the default static branch prediction mechanism to be used, which is: if the conditional jump instruction is jump backward, the prediction is "jump", and if it is a conditional jump instruction that jumps forward, it is predicted as "do not jump". And the RISC-V architecture requires the compiler to compile and generate assembly code according to this default static branch prediction mechanism, so that the low-end CPU can also get good performance.

To make the hardware design as simple as possible, the RISC-V architecture specifically defines all the offsets of the conditional jump instruction jump Target (relative to the address of the current instruction) as a signed number, and its sign bit is encoded in a fixed position. Therefore, this static prediction mechanism is very easy to implement in hardware, the hardware decoder can easily find the fixed position, and determine whether it is 0 or one to determine whether it is a positive or negative, if a negative number is the target address of the jump to the current address minus the offset, that is, jump backward, the prediction is "jump". Of course, for high-end CPUs equipped with a hardware branch predictor, advanced Dynamic Branch prediction mechanisms can be used to ensure performance. Concise subroutine invocation

In order to understand this section, the process of calling a subroutine in a general RISC architecture is described in the following procedure:

• After entering the sub-function, a memory write (Store) instruction is required to store the current context (the value of the universal Register, etc.) in the stack area of the system memory, which is often referred to as the "save Site".
• At the time of exiting the subroutine, a memory read (Load) instruction is required to read the previously saved context (the value of the universal Register, etc.) from the stack area of the system memory, which is often referred to as the "recovery site".

The process of "saving the scene" and "Recovering the scene" is usually done by a compiler-generated instruction, and developers using high-level languages such as C or C + + should not be too concerned about it. High-level language program directly write a sub-function call, but the bottom of the "Save the scene" and "recovery site" process is actually happening (from the compiled assembly language to see those "Save the scene" and "recovery site" assembly instructions), It also requires a number of CPU execution times to be consumed.

To speed up the process of "saving the scene" and "Recovering the scene", some RISC architectures have invented instructions to write multiple registers to memory (Store multiple) at once, or to read multiple registers out of memory (Load multiple) at a time. The benefit of such directives is that a single instruction can accomplish many things, thus reducing the amount of code in the assembly instruction and saving the size of the code. However, the disadvantage of this kind of "Load multiple" and "Store multiple" is that the hardware design of the CPU will be complicated, increase the overhead of hardware, and possibly damage the timing of the CPU can not improve the frequency, the author in the design of such a processor is suffering.

The RISC-V schema discards the use of this "Load multiple" and "Store multiple" instructions. and explain that if there are occasions where the number of instructions for this "save site" and "recovery site" is more than that, then a common library (dedicated to saving and recovering the site) can be used to eliminate the "Save the Field" and "restore site" instructions that are placed in the process of each child function call.

This choice once again confirms Risc-v's philosophy of pursuing hardware simplicity, because abandoning the "Load multiple" and "Store multiple" instructions can greatly simplify the hardware design of the CPU, and for low-power, small-area CPUs to choose a very simple circuit to implement, High-performance hyper-scalar processors due to the strong hardware dynamic scheduling ability, can have a powerful branch prediction circuit to ensure that the CPU can quickly jump execution, so that you can choose to use a common library (dedicated to save and restore the site) in a way to reduce the amount of code, but at the same time achieve high performance. Unconditional Code Execution

Many of the earlier RISC architectures invented instructions with conditional codes, such as the first few in the instruction code that indicated a conditional code (Conditional code), which was actually executed only if the condition of the code corresponds to the true condition.

This form of encoding the condition code into the instruction allows the compiler to compile short loops into instructions with conditional codes instead of compiling the component branch jump instructions. This reduces the presence of branch jumps, reduces the number of instructions on the one hand, and avoids the performance penalty caused by branch jumps. However, the disadvantage of this "conditional code" Directive will also make the CPU hardware design become complex, increase the cost of hardware, may also damage the timing of the CPU can not improve the frequency, the author in the design of such a processor is suffering.

The RISC-V schema discards the use of this "conditional code" directive, and uses normal conditional branch jump directives for any conditional judgment. This choice once again confirms the risc-v pursuit of hardware simple philosophy, because the way to abandon the "conditional code" command can greatly simplify the CPU hardware design, for low-power small area of the CPU can choose very simple circuit implementation, and high-performance ultra-scalar processors due to the hardware dynamic scheduling ability is very strong, The powerful branch predictive circuitry ensures that the CPU can perform fast jump execution to achieve high performance. No Branch delay slots

Many of the early RISC architectures use "Branch delay Slots", the most representative of which is the MIPS architecture, and in many classical computer architecture textbooks, the branch delay slots are introduced using MIPS. A branch delay slot is one or more instructions immediately following each branch instruction that is not affected by the branch jump, and the following instructions are bound to be executed, regardless of whether the branch jumps or not.

Many of the early RISC architectures were created by branching delay slots because of the simplicity of the processor pipeline at the time, and the fact that the advanced hardware Dynamic branch Predictor was not used, so it was possible to achieve considerable performance with branch delay slots. However, this branch delay slot makes the CPU hardware design extremely awkward, CPU designers are often miserable.

The RISC-V architecture abandons the branch delay slot, once again confirming Risc-v's philosophy of simplifying hardware, since the modern high-performance processor's branch prediction algorithm has a very high precision and can have a powerful branch prediction circuit to ensure that the CPU can accurately predict jump execution to achieve high performance. For low-power, small-area CPUs, the hardware is greatly simplified due to the absence of support for branch delay slots, which can further reduce power consumption and improve timing. No zero overhead hardware loops

Many RISC architectures also support the 0 overhead hardware loop (Zero Overhead Hardware Loop) instruction, which is thought to be directly involved with the hardware by setting some loop count registers (loop counts) and then allowing the program to loop automatically. Loop count automatically minus 1 per loop, so that the loop is exited until the value of loop count becomes 0.

The 0 overhead loops that are proposed to invent this kind of hardware assistance are because of the for loop in the software code (for i=0; i<= "p=" "></N;>

There will be a loss, this type of 0 overhead hardware loop instruction greatly increases the complexity of hardware design. Therefore, the 0 overhead loop instruction is completely opposite to the philosophy of simplifying hardware in the RISC-V architecture, which naturally does not use such 0 overhead hardware loop instructions in the RISC-V architecture. Concise Operation Instructions

As mentioned in section 2.1 of this chapter, the RISC-V architecture uses a modular approach to organizing different sets of instructions, and the most basic subset of integer instructions (i-letter representations) supports operations including addition, subtraction, SHIFT, bitwise-logical operations, and comparison operations. These basic operations can perform more complex operations (such as multiplication and floating-point operations) through a combination or library of functions, enabling most software operations to be performed.

The operations supported by the integer multiplication instruction subset (M-letter representation) include symbolic or unsigned multiplication and division operations. The multiplication operation can support two 32-bit integer multiplication to get a 64-bit result; The division operation can support two 32-bit integers to divide the remainder of a 32-bit quotient with 32 bits.

The single-precision floating-point instruction subset (F-letter) and the double-precision floating-point instruction subset (d-Letter representation) support operations including floating-point addition and subtraction, multiplication, multiply-accumulate, square-root and compare, and provide integer-to-floating-point, single-precision and double-precision floating-point format conversion operations.

Many RISC-architecture processors produce software anomalies when the operation instruction generates errors such as overflow (Overflow), underflow (underflow), denormalized floating point (subnormal), and 0 (Divide by Zero). A special feature of the RISC-V architecture is that no exception is generated for any of the arithmetic instruction errors (both integers and floating point instructions), but rather a special default value is generated, and the state bits of some state registers are set. The RISC-V architecture recommendation software uses other methods to find these errors. Again, it clearly reflects the risc-v architecture's attempt to simplify the basic instruction set, simplifying the philosophy of hardware design.

Graceful Compression Instruction Subset

The basic risc-v Basic integer instruction subset (letter i) specifies that the instruction length is equal to 32 bits, and this equal-length instruction definition makes the basic RISC-V CPU, which supports only a subset of integer instructions, very easy to design. But equal-length 32-bit coding instructions can also cause a relatively large code size problem.

To satisfy certain scenarios where code volume requirements are high (such as the embedded domain), risc-v defines an optional subset of compression (compressed) instructions, denoted by the letter C, or by RVC. Risc-v has the advantage of the latter, from the outset to plan the compression instructions, reserved enough coding space, 16-bit long instructions and ordinary 32-bit long instructions can be seamlessly intertwined, the processor also does not define the additional state.

Another special point of the risc-v compression directive is that the compression strategy for 16-bit instructions is to compress the information in a subset of the most commonly used 32-bit instructions (for example, assuming that an instruction uses two of the same operand index, you can omit the encoding space for one of the indexes), Therefore, each 16-bit long instruction can find its corresponding original 32-bit instruction. As a result, program compilation becomes a compression instruction that can be done only at the assembler stage, greatly simplifying the burden on the compiler toolchain.

The RISC-V architecture researchers conducted detailed code volume analysis, 3 shows that the RV32C code volume is reduced by 40% compared to the RV32 code size, and has a good performance compared to the arm,mips and x86 architectures, according to the analysis results.

Figure 3 Code density comparison for each instruction set architecture (smaller data better) privileged mode

The RISC-V architecture defines three modes of operation, also known as privileged mode (privileged modes):

• Machine mode: The model, called M mode.
• Supervisor mode: Supervisory model, referred to as S mode.
• User mode: username, referred to as U modes.

The RISC-V schema defines M mode as the required mode, and the other two are selectable modes. Different systems can be implemented with different combinations of patterns.

The RISC-V architecture also supports several different memory address management mechanisms, including the management of physical addresses and virtual addresses, enabling the RISC-V architecture to support a wide range of systems from simple embedded systems (direct manipulation of physical addresses) to complex operating systems (direct manipulation of virtual addresses). CSR Register

The RISC-V architecture defines a number of control and status registers that are used to configure or record some of the state of the operation. A CSR register is a register inside a processor core that has no relationship with its own address-coded space and memory-addressable address range.

The CSR registers are accessed using dedicated CSR directives, including CSRRW, Csrrs, CSRRC, Csrrwi, Csrrsi, and csrrci directives. Interrupts and exceptions

Interrupts and anomaly mechanisms are often the most complex and critical parts of the processor instruction set architecture. The RISC-V architecture defines a relatively simple set of interrupt and exception mechanisms, but it also allows users to customize and extend them. Vector instruction Subset

RISC-V Architecture currently has no training vector (vector) instruction subset, but from the current draft can be seen, risc-v vector instruction subset design concept is very advanced, due to the advantages of the latter and the use of vector architecture for many years to develop the conclusion of maturity, The RISC-V architecture will use variable-length vectors instead of vector-length SIMD instruction sets (such as ARM's neon and Intel's MMX), enabling flexibility to support different implementations. CPUs that pursue low-power, small areas can choose to use short-length hardware vectors, while high-performance CPUs can be implemented with long hardware vectors, and the same software code can be compatible with each other. Self-customizing instruction extensions

In addition to the extensible and selectable subset of the modular instructions described above, the RISC-V architecture also has a very important feature, which is the support of third-party extensions. Users can extend their own subset of instructions, RISC-V reserved A large number of instruction encoding space for the user's custom extension, but also defined four custom instructions for users to use directly, each custom instruction has a few bits of sub-encoded space reserved, therefore, The user can extend dozens of custom instructions directly using the four custom instructions. Summary and comparison

Processor design Technology After decades of evolution, with the development of large-scale integrated circuit design technology to today, showing the following characteristics:

• Because the hardware scheduling capability of the high-performance processor is very strong and the frequency is very high, the hardware design expects the instruction set to be as neat and simple as possible, so that the processor can design a higher frequency and lower area.
• Extremely low power processors based on IoT applications are more demanding low power and low area.
• Memory resources are also richer than earlier RISC processors.

As a result of these factors, many of the early RISC architecture design concepts (based on the technical background of the time), today not only can not help modern processor design, but become a burden of shackles. Some of the features defined by the early RISC architecture, on the one hand, make the hardware design of the high-performance processor shackled; On the other hand, the very low-power processor hardware design carries unnecessary complexity.

Thanks to its post-advantage, the new RISC-V architecture can circumvent all these known burdens, while using its advanced design philosophy to design a "modern" set of instructions. This section again summarizes its features as shown in table 2.

Table 2 Summary of RISC-V instruction set architecture features

[Go] risc-v Architecture Introduction