GPIO configuration ODR, BSRR, BRR detailed

STM32 GPIO configuration ODR, BSRR, BRR detailed

Using the Stm32 configuration Gpio to control the LED display state, the ODR,BSRR,BRR can be directly used to control the PIN output status.

The ODR register is readable and writable: Both the control pin is high and the pin is low-level.

Pin for bit write 1 Gpio pin High, write 0 low

BSRR write-only registers: [color=red] can control both the pin and the low level of the pins.
To register high 16bit write 1 corresponding pin is low, register low 16bit write 1 corresponding pin is high. Write 0, no action

BRR Write register only: The PIN status can only be changed to low level, the register pin for bit write 1 corresponding pin will be low. Write 0 no action.

At first, perhaps you have the following doubts as I do:

1. Why do I need BSRR and SRR registers for the ODR to control the pin high and low level?
2. Why do I need the SRR register if BSRR can achieve the full functionality of the BRR?

For question 1------The answer to STMicroelectronics is---

"This-to, there is no risk-an IRQ occurs between the read and the Modify access."
What do you mean? It is when you use BSRR and BRR to change the state of the pin, there is no risk of interruption. There is no need to turn off interrupts.

The pseudo-code that uses the ODR to manipulate Gpio is as follows:

DISABLE_IRQ ()
Save_gpio_pin_sate = Read_gpio_pin_state ();
Save_gpio_pin_sate = xxxx;
Chang_gpio_pin_state (save_gpio_pin_sate);
ENABLE_IRQ ();

Closing interrupts can significantly delay or lose the capture of an event, so it is best to control the Gpio state with SBRR and BRR

For question 2-------personal experience to judge STMicroelectronics is simply for programmer's convenience to estimate what to do.

Because the low 16bsts of BSRR happens to be a set operation, and a high 16bit is the reset operation and the BRR low 16bits is the reset operation.

Simply put, the high 16 bits of GPIOX_BSRR are called clear registers, while the low 16 bits of GPIOX_BSRR are called set registers.

The other register GPIOX_BRR only has a low 16-bit effect and has the same functionality as the GPIOX_BSRR high 16-bit.

Give an example of how to use these two registers and the advantages embodied.

For example, the Gpioe 16 io is set to output, and each operation requires only

Change the low 8-bit data to remain high by 8 bits, assuming that the new 8-bit data is in the variable NewData,

This requirement can be implemented by operating these two registers, which have two functions in the STM32 firmware library.

Gpio_setbits () and gpio_resetbits () use these two register operation ports.

The above requirements can be implemented as follows:

Gpio_setbits (Gpioe, NewData & 0xff);
Gpio_resetbits (Gpioe, (~newdata & 0xFF));

You can also directly manipulate the two registers:

GPIOE->BSRR = NewData & 0xFF;
GPIOE->BRR = ~newdata & 0xFF;

Of course, you can also do 8-bit operations at one time:

GPIOE->BSRR = (NewData & 0xff) | ((~newdata & 0xff) <<16);

Of course, you can also do 16-bit operations at one time:

GPIOE->BSRR = (NewData & 0xFFFF) | ((~newdata) <<16);

From the last operation you can see that using the BSRR register, you can implement simultaneous modification of 8 port bits.

Someone asked if BSRR's high 16-bit is superfluous, take a look at the following example:

If you want to gpioe the bit 7 ' 1 ' and bit 6 ' 0 ' in an operation, it is very convenient to use BSRR:
GPIOE->BSRR = 0x400080;

If there is no high 16 bits of BSRR, then 2 operations, resulting in bit 7 and bit 6 changes are not synchronized!
GPIOE->BSRR = 0x80;
GPIOE->BRR = 0x40;

Another feature of BSRR is that set is higher than the reset level,

That means the same bit does set and reset, and the end result is set.

To synchronize changes as long as the simple GPIOX->BSRR = 0xffff0000 | PATTEN;

No need to consider which needs to set 1, which needs to be zeroed

From the last operation you can see that using the BSRR register, you can implement simultaneous modification of 8 port bits.

Http://www.cnblogs.com/shangdawei/p/4723941.html

GPIO configuration ODR, BSRR, BRR detailed