Q: Why should I consider driving capacitive load issues?
A: This is usually not a choice. In most cases, the load capacitance is not artificially added to the capacitor. It is often an objective existence that people do not want, such as the capacitive effect shown by a coaxial cable. In some cases, however, it is required to decouple the DC voltage at the output of the op amp. For example, when the op amp is used as an inverted phase of a reference voltage or when driving a dynamic load. In this case, you may connect the bypass capacitor directly to the output of the op amp. In either case, the capacitive load has an impact on the performance of the OP amp.
Q: How does capacitive load affect op amp performance?
A: For simplicity, the amplifier can be seen as an oscillator. Each op amp has an internal output
Resistance RO, when it is connected to the capacitive load, an additional pole is generated on the OP amp transfer function. The amplitude-frequency characteristic curve of positive 1 (b) Baud graph shows that the amplitude-frequency characteristic slope of the additional pole is more than that of the main pole 20db/10 times octave. As can be seen from the phase-frequency characteristic curve 1 (c), the phase shift of each additional pole increases -90°. We can use Figure 1 (b) or Figure 1 (c) to determine the stability of the circuit. As can be seen from Figure 1 (b), the circuit is unstable when the sum of the open-loop gain and feedback attenuation is greater than 1 o'clock. Similarly, in Figure 1 (c), if a working frequency is lower than the closed-loop bandwidth, the OP amp will oscillate when the loop phase shift exceeds -180° at this frequency. The closed-loop bandwidth of the voltage-feedback op amp (VFA) equals the op-amp gain bandwidth product (
GBP, or unity gain frequency) divided by the circuit closed-loop gain (A CL). The phase margin of an op amp circuit is defined as the additional phase shift (i.e., the loop phase shift ten phase margin =-180°) that corresponds to the closed-loop bandwidth required for circuit instability. When the phase margin is 0 o'clock, the loop phase shifts to -180°, and the discharge path is unstable. Typically, problems occur when the phase margin is less than 45 °, such as the frequency Response "spike", overshoot in step response, or "ringing". To make room for the phase margin, the additional poles generated by the capacitive load should be at least 10 times times higher than the closed-loop bandwidth of the circuit, if not so the circuit may be unstable.
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Hardware 100,000 Why--op release (eight) op amp capacitive load Drive problem