(corrected) This problem includes the hardware structure of the CPU and the category of assembly language. Here, comb it.
First of all, the main "Li Jianguo" self-answer part of the question is said to be correct,
the instruction set of the CPU is the interface between the two tiers of software and CPU, and the CPU itself is the "instantiation" of this set of CPU instructions..
No matter how advanced the software is in the upper level, want to execute in the CPU, it must be translated into "machine code", translation this work is executed by the compiler. In this process, the compiler will go through "compile", "assemble", "link" several steps, and finally generate "executable". The binary machine code is saved in the executable file. This string of machine code can be read and executed directly by the CPU.
In software sense, "instruction set" is actually a specification, specification of the Assembly of the file format.
The following is a x86 assembly code:
mov word ptr es:[eax + ecx * 8 + 0x11223344], 0x12345678
Here you can show the format limits of the instruction set:
1. You can use the MOV instruction, but it only has 2 operands.
2. Its operand length is (word), do not see the back 0x12345678 is considered to be a 32-bit operand.
3. It has a paragraph beyond the prefix, where es is used, you can also use DS, CS, SS, FS, GS. But only with these few.
4. The first operand is a memory address and the second is an immediate number. However, this memory address can not be written in a random, written [eax+ecx*10+0x11223344] is wrong.
As a matter of fact
A assembly instruction corresponds to a machine code of one by one.The above sinks can be translated by the x86 compiler into almost the only piece of machine code:
C7 C8 44 33 22 11 78 56
The above mentioned 1,2,3,4 point if there is a mistake, this step will fail.
As you can see, the function of the instruction set is to tell the programmer/compiler that the assembly must be formatted. What instructions are supported, what restrictions are imposed, what operands are used, and what addresses are the contents of the instruction set specification, which, if written incorrectly, cannot be translated into machine code.
Instruction Set specification compilation, assembly can be translated into machine code, machine code tells the CPU what to do each cycle. So
The CPU instruction set is a set of functions that describe what the CPU can achieve, that is, the set of "which machine code the CPU can use".
What does the machine code do after it enters the CPU?
===================== the compiler and CPU boundaries ========================
The machine code that needs to be executed is first to be dispatched by the OS to the memory, when the program executes, the machine code goes through the MEMORY--CACHE--CPU fetch, enters the CPU pipeline, then decodes it, the decoding work is generated like the CPU internal data format, microcode (or similar format , this format will be designed by different vendors).
This process is drawn as a graph:
Software Layer: assembly language
------------------------------------------------------------------------
Interface: the machine code corresponding to assembly language
------------------------------------------------------------------------
Hardware layer: CPU uses internal data structure for operation
If the machine code represents the function is within the instruction set specification, this machine code can produce microcode, and the normal flow within the CPU. Assuming that the machine code is wrong, it is not possible to pass the decoding phase of the CPU, the control circuit will be error. This situation is reflected in Windows is often a blue screen, because the CPU can not continue to execute, it even the next instruction is not known anywhere.
then the instruction set is represented in the CPU: only instructions within the CPU instruction set can be successfully decoded and sent to the CPU pipelining backend to execute.
Unlike conventional ideas, CPUs do not require any form of storage media to store instruction sets, because the "decode" step is to decode the code in the instruction set. On the hardware, decoding this thing requires a large number of logical gate arrays to be implemented.
Look beyond the format of this circle to see the problem. It can be said that the capacity of the CPU execution unit determines the scope of the instruction set. For example, the execution unit of the CPU has the ability to perform 16-bit addition, 32-bit addition, 64-bit addition, then the instruction set
GeneralThere will be an add, add, and add 64 expression. If the execution unit of the CPU does not have a circuit to perform the AVX instruction, then the instruction set
GeneralThere is no such command to use VINSERTF128. Therefore, a powerful execution unit can provide more instruction sets.
Then look at the question "where is the CPU instruction set", and the answer is,
The CPU itself is the CPU instruction set. The instruction set specifies what the CPU can do, and the CPU is the tool for doing it specifically. If you must specify a narrow set of CPU instructions to place. That's the "decoding circuit" in the CPU.edited on 2014-04-21 10 reviews Thanks for sharing collection • No help · Report Agree objection, will not show your nameCascadeusers, Zhu Suzan, Tan Yu and other people agree Yes, this explanation is a bit long. Be patient
Modern CPU has not been removed, I only in the computer composition principle experiment class with VHDL on an experimental platform to do a simulated CPU. For example, you may have a better understanding.
For example, we design a set of instructions, which must have an addition instruction. such as add R1 R2. We can assume that this instruction means calculating the contents of the register R1 and R2, and then depositing the result in the R1 register.
Then after compiling this instruction will become binary, such as 010100010010. This binary instruction altogether 12 bits. Can obviously be divided into three parts. The first 0101 indicates that this is an addition instruction, followed by 0001 is said to be register 1, the last 0010 is the second number is register 2 (actually there is no such a simple instruction, at least should distinguish between the operand is register or direct data, But in order to make this easier to understand, it is simplified). We can enter this instruction into a CPU with 12 wires. Wire power is 1, no power is 0. For the sake of narration, we use A0-A11 to make the 12 wires numbered from left to right.
The computer then parses the instruction. The steps are as follows:
- At the very beginning of the two conductors A0 and A1, the first one has electricity, the second is no power, you can know that this is an operation instruction (not a memory operation or a jump, etc.). Then the instruction will be fed into the logic unit (ALU) to calculate. It's actually very simple. As long as these two wires control the next part of the circuit switch.
- The next A2 and a3,01 represent addition, then go to the addition operation that part of the circuit, turn off the calculation circuit such as subtraction.
- The A4-A7 will be fed into the Register circuit to read the value saved by the register. To the first data interface circuit of the ALU.
- The rear a8-a11 is also fed into the register selector circuit, the R2 register is switched on, and the value is sent out to the second data interface of the Alu R2.
- The ALU starts the operation, adds the data on the two interface circuits, and then outputs them.
- The final result was sent back to R1.
Basically the simple arithmetic computer is the operation of this. He doesn't really know what your instructions mean. The specific instruction programming machine code will become the digital circuit switch signal. Some of these segments act as control signals and control other parts of the data by taking different circuits to perform the operation. He doesn't have a place to keep a dictionary of how these machine codes are translated, and the meaning of all machine codes is embodied in the design of the whole circuit.
Of course, from the assembly to the machine code this step is the assembler translation. The assembler, of course, knows what kind of machine code to translate an instruction into.
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The highest-rated (@Cascade) answer should be how the instructions are executed, and where the CPU exists for the instruction set of the main question, my answer is:
1. The instruction set is specified in the design of the CPU, and the instruction set specifies which of the CPUs can execute "instructions" that are legal.
2. The instruction set is a collection of functions that are embodied in each "instruction" that can be executed. When it comes to specific instructions, it involves who is the "operand", and "how to find the operand" and "what to do with the action object".
3. The function of the instruction is realized by the function logic circuit in the CPU, and the previous "instruction design" determines how to carry out "logic circuit design". The same instructions can take different logic circuit designs.
4. Because the "instruction set" itself is not functional, so in the CPU you can not find the "instruction set" this entity, but the instructions in the instruction set and the CPU of the internal transistor composed of logic circuit is equivalent (in addition to the instruction part of the interrupt, peripherals, such as these are not considered), then the equivalent of the non-equivalence, Is the whole transistor logic circuit that implements the instructions in the instruction set.
5. If you want to find its instruction set without giving the CPU of the instruction set, you can test the function of each instruction encoding by modifying the contents of the next instruction that the PC points to, and observing the changes in memory and registers (which is obviously of little practical value) (You can use this method to understand the function of the command).
Hardware structure and assembly language of CPU
