Hello Eight (i) 2812EV Module---Universal timer _ work

The capabilities of the event manager

2812 with two event manager modules Eva and eVB, each EV module has 2 Universal timers, 3 comparison units, 3 capture units, and 1 orthogonal coded circuits.

(The blue Word in the table indicates that the signal is low level effective)

The universal timer is used for timing, and each timer also generates 1 independent PWM waveforms;

The main function of the comparison unit is to generate the PWM waveform, Eva has 3 comparison units, each unit can generate a pair (two-way) complementary PWM waveform, generated 6-channel PWM waveform just can drive a three-phase bridge circuit.

The function of the capturing unit is to capture the ascending or descending edge of the external input pulse waveform, to calculate the pulse interval, and to count the number of pulses.

The orthogonal coded circuit can encode and count the input orthogonal pulses, which can be connected with the photoelectric encoder to obtain the position and velocity of the rotating machine parts.

(1) External compare-output Trip inputs-We can understand to cut off the output of the external control input, to C1trip as an example, when the comparison Unit 1 work, its two pins PWM1 and PWM2 are constantly output PWM waveform, this time, If the c1trip signal into a low level, then PWM1 and PWM2 pins are placed into a high resistance state, there will be no PWM waveform output, that is, in this pin input low level, then the comparison output will be cut off.

(2) External Timer-compare trip inputs-We can understand to cut off the timer to compare the output of the external control input, to t1pwm_1cmp for example, when the Timer 1 comparison function in operation, and the T1PWM pin output PWM waveform, At this time if the T1ctrip pin signal to a low level, then the PIN state is set to a high level, there will be no more PWM waveform output.

(3) The Pdpintx (x=a or B) of the External trip inputs is actually a power-driven protection that provides protection for the security of the system, for example, if a voltage, current, or temperature surge occurs in the circuit, if the pdpintx interruption is not blocked, When the Pdpintx pins become low power, 2812 of all the PWM output pins will become high impedance, thus preventing further damage to the circuit to protect the system. Of course Pdpintx in the circuit design should be given to it with a monitoring circuit status signal.

1. General Timer---with General timer 1 as an example

EV Event Manager Clock module

General Timer Module structure

Common registers associated with T1

T1 Cycle Register----T1PR 1 6-bit
T1 Comparison Register----T1CMPR 1 6-bit
T1 Count Register----t1cnt 1 6-bit
T1 Control Register----T1con 1 6-bit

Global Timer Control Register a----Gptcona 1 6 bits

Common input signals for T1

Internal clocks from the CPU
The external clock input Tclkina, the maximum frequency is 1/4 of the device's own clock, namely 1/4*150m
tdira/b, for timer increment/decrement counting mode

Reset Signal Reset

Output signal of T1

Comparison of timer output t1pwm_t1cmp
Ad conversion boot signal to ADC module
Underflow, overflow, comparison matching and periodic matching signals
Count direction indicator

Shadow Register action---overload condition

You can write new values to T1CMPR or T1PR at any point in a cycle, assuming we want to write a new numeric 0xXXXXh to T1CMPR, which first writes the value to the T1CMPR shadow Register, When a specific event specified by the 3rd-bit TCLD1 and 2nd-bit TCLD0 in T1con occurs, the shadow register's data is written to the T1CMPR work register.

Write new data to the T1PR 0xXXXXh, the data will be immediately written to the shadow register, only when the t1cnt completes this cycle count, the value is 0, the Shadow register contents will be loaded into the work register, thus changing the T1PR value.

Timer comparison Register overload condition
TCLD1 TCLD0
0 0 when the counter t1cnt value is 0

0 1 when the counter t1cnt value is 0 or equal to the period register
1 0 Load immediately
1 1 Reservations

The counting mode of the timer---determined by the T1con 12th 11-bit

TMODE1 TMODE0
0 0 Stop/Hold
0 1 Continuous increase/decrease mode
1 0 Continuous growth mode

1 1 directional Add/Subtract count mode (directional up/down count mode)

Continuous increment/Subtraction Technology model-----The actual counting period is 2*T1PR

Continuous increment mode-----The actual counting period is t1pr+1

Directional increase or subtraction counting mode

T1cnt to count or decrement, depending on the level of the pin Tdira, if the Tdira is high, then t1cnt to increase the count; If the Tdira is low, then the t1cnt is minus count. If the Tdira level has changed during the counting process, the counting direction must change when the next CPU clock cycle is completed after the current counting cycle.

T1-related interrupts

Overflow interrupt t1ofint, underflow interrupt t1ufint, compare interrupt T1cint, cycle interrupt T1pint

(1) When the value of the t1cnt 0xFFFFh, the occurrence of the timer T1 overflow interrupt. When an overflow event occurs, and then over 1 CPU clock cycles, the flag bit of the overflow interrupt is placed.

(2) When the value of the t1cnt is 0x0000h, a timer T1 overflow interruption occurs. After the current overflow event occurs, there are 1 CPU clock cycles, then the flag bit of the underflow interrupt is placed.

(3) When the value of the t1cnt is equal to the value of the T1 comparison register T1CMPR, the comparison of the timer T1 is interrupted. When a comparison match occurs, then there are 1 CPU clock cycles, then the interrupt flag bit is reset.

(4) When the value of the t1cnt is equal to the value of the T1 periodic register T1PR, the periodic interruption of the timer T1 occurs. When a cycle event occurs, there are 1 CPU clock cycles, and the flag bits of the cycle interrupt are placed.

If the interrupt has been enabled, the interrupt request will be sent as the pie module when the bit of the interrupt is placed. When exiting interrupts, be sure to manually clear the bits of the peripheral interrupt flag. In EV, the registers associated with the above interrupts are Evaifra, Evaimra, EVAIFRB, EVAIMRB

In addition to being able to produce interrupts, the above event can also produce a ADSOC signal, which is to start the ad conversion signal, so that it can periodically start the ad conversion. Depending on the 8th and 7th digits of the Register Gptcona, the advantage of this feature is that it allows the event of the universal timer to be synchronized with the ADC startup conversion without interference from the CPU

The correlation bit (T1TOADC) of the signal in the Gptcona that T1 initiates the ad conversion
Bit8 bit7
0 0 does not start ADC
0 1 underflow Interrupt start ADC
1 0 Cycle Interrupt start ADC
1 1 Compare interrupt start ADC

Synchronization of Timers

T2 can use T1 periodic registers to ignore their own periodic registers, or you can use the T1 to enable the T2 count, which ensures that T1 and T2 can achieve the synchronization count

1. The t2swt1 of T2con is set to 1, and the T1con tenable bit is implemented to start the Universal Timer 2 count so that two counters (T1, T2) can start the count at the same time.

2. Initializes different values for t1cnt and t2cnt.

3. The SELT1PR of T2con is set to 1, and the timer 2 is specified as the periodic register of the timer 1.

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