How to calculate vswitch backboard bandwidth

How to calculate the bandwidth of A vswitch's backboard is the maximum amount of data that can be transferred between the vswitch interface processor, interface card, and data bus. The bandwidth indicates the total data exchange capability of a vswitch. The unit is Gbps. It is also called the switching bandwidth. The bandwidth of A vswitch ranges from several Gbps to hundreds of Gbps. The higher the bandwidth of A vswitch, the stronger the ability to process data, but the higher the design cost. Generally, the calculation method of www.2cto.com is as follows: 1) Evaluate the bandwidth of the wire speed backboard to check the total bandwidth that can be provided by all ports on the switch. The formula is as follows: number of ports * corresponding port rate * 2 (full duplex mode). If the total bandwidth is less than or equal to the nominal backboard bandwidth, the bandwidth is linear. 2) Layer 2 packet forwarding speed Layer 2 packet forwarding rate = number of Gigabit ports x 1. 488 Mpps + 0.1488 MB port count * Mpps + number of other types of ports * Calculation Method. If this rate can be less than or equal to the forwarding rate of a nominal L2 packet, the switch can achieve the line speed when performing Layer 2 switching. 3) layer-3 packet forwarding speed Layer-3 packet forwarding rate = number of Gigabit ports x 1. 488 Mpps + 0.1488 MB port count * Mpps + number of other types of ports * Calculation Method. If this rate can be less than or equal to the forwarding rate of a nominal three-tier packet, the switch can achieve line speed when performing layer-3 switching. Www.2cto.com, how does 1.488Mpps get it? The packet forwarding speed is measured by the number of 64 bytes of data packets (minimum packet) sent per unit time. For Gigabit Ethernet, the calculation method is as follows: 1,000,000,000 bps/8bit/(64 + 8 + 12) byte = 1,488,095 pps Description: When the Ethernet frame is 64 bytes, the fixed overhead of the frame gap between 8-byte frames and 12-byte frames must be considered. Therefore, the packet forwarding rate of a Gigabit Ethernet port with a line speed is 1.488 Mpps when a 64 byte packet is forwarded. The line-rate port forwarding rate of Fast Ethernet is exactly 148.8 of that of Gigabit Ethernet, which is kpps. * For 10-Gigabit Ethernet, the packet forwarding rate of a wire speed port is 14.88 Mpps. * For Gigabit Ethernet, the packet forwarding rate of a wire speed port is 1.488 Mpps. * For fast Ethernet, the packet forwarding rate of a wire speed port is 0.1488 Mpps. * For the POS port of the OC-12, the packet forwarding rate of a wire speed port is 1.17 Mpps. * For the POS port of the OC-48, the packet forwarding rate of a wire speed port is 468 MppS. Therefore, if the above three conditions can be met, we will say that this switch truly achieves linear non-blocking backboard bandwidth resource utilization is closely related to the internal structure of the switch. Currently, the internal structure of a vswitch mainly includes the following types: first, the shared memory structure, which relies on the central switching engine to provide full-Port High-Performance connections, the core engine checks each input packet to determine the route. This method requires a lot of memory bandwidth and high management costs. Especially with the increase of switch ports, the price of the central memory will be very high. Therefore, switching the machine kernel becomes a bottleneck for performance implementation; the second is the cross-bus structure. It can establish direct point-to-point connections between ports, which is good for single-point transmission performance, but not suitable for multi-point transmission. The third is the hybrid cross-bus structure, this is a hybrid cross-bus implementation method. Its design idea is to divide an integrated cross-Bus Matrix into small cross matrices and connect them through a high-performance bus in the middle. The advantage is that the number of Cross buses is reduced, the cost is reduced, and the bus contention is reduced. However, the bus connected to the cross matrix becomes a new performance bottleneck.