How to set memory inside the BIOS

Above 1MB Memory Test: Sets whether 1M or more memory is detected at post. This option has been eliminated in the new BIOS. As memory prices plummeted, computer users installed memory capacity of the sudden increase in the power-on when the bulk memory self-test time is too long, in the future, even if the memory test may also appear allow/prohibit switch.

Auto Configuration: When set to allow, the BIOS is set according to the best state. The BIOS can automatically set memory timing, so some modifications to the memory settings are prohibited, and it is recommended that you choose the allowed method.

Memory Test Tick Sound: Whether to emit a click sound for a memory self-test. If you're bored with it, you can turn them off.

Memory Parity Error Check: Sets whether to set up memory parity. More in the 30-line memory use ERA, has been eliminated. However, forcing the non parity memory to the parity setting will cause the computer to fail to boot.

Cache Memory Controller: whether to use the cache. Not used in the popular award BIOS.

Shadow RAM Option: Set the system BIOS or display card BIOS to map to normal memory. Can speed up, but may also cause a panic.

Internal Cache Memory: Whether to use CPU internal caching (first-level caching). can improve system performance.

External Cache Memory: Whether to use the CPU external cache (level two cache on the motherboard). can improve system performance. The advent of AMD's new CPU with level two caching has relegated the two-level cache on the motherboard to a three-level cache.

Concurrent refresh: Literal translation is the simultaneous occurrence of a refresh. Setting the CPU to refresh the memory at the same time for other I/O operations can improve system performance.

DRAM Read Wait state: Sets the waiting clock cycle for the CPU to read data from memory. More waits can be set when memory is slower than the CPU.

DRAM Write Wait state: Sets the waiting clock cycle for the CPU to write data to memory. More waits can be set when memory is slower than the CPU.

Slow Refresh: For good quality memory, keep the data for a long time, you can set a longer time period, thereby improving system performance.

Shadow cachecable: Adds a cache to the BIOS ROM mapped to conventional memory to further improve performance.

Page mode: Makes the memory work in page mode or page interleaved modes.

RAS Timeout Counter: Makes page mode or page interleaved mode work faster. Because it is possible to exceed the memory RAS cycle, a counter is used to monitor the RAS cycle and, once the RAS cycle is exceeded, the cycle is automatically reset to 0.

Memory Relocation: Memory relocation. The 384 upper memory (Upper Memory block) data is dumped into extended memory above 1MB.

Memory Hole: Someone called a memory hole. The area where the memory address is 15MB-16MB is left to some special ISA expansion cards to speed up or avoid collisions with the card. is generally set to prohibit unless the ISA expansion card has a specific description.

Drma Timing Setting: Fast page memory or Edo memory speed setting, usually 60ns or 70ns selection, invalid for 10ns or faster SDRAM memory.

Fast MA to RAS Delay: Sets the latency between memory addresses (Memory address) and Memory line address trigger (RAS).

DRAM Write Brust Timing:cpu writes data such as cache, and then writes the latency of memory.

Fast RAS to CAS Delay: The delay time between the line address trigger signal and the column address trigger signal. Usually the ras# drops down to cas# between the time.

DRAM Lead-off the time before TIMING:CPU read/write memory.

DRAM Speculative read: When set to allow, the time spent reading memory is one time period ahead of normal time, which can improve system performance.

DRAM Data Integrity Mode: Select the memory check mode is parity or ECC.

Refresh RAS Assertion: Sets the row address refresh time period for memory, which can delay refreshing for good quality memory, thereby improving system performance.

RAS Recharge Period: The amount of time required to recharge a memory line address signal.

Fast EDO Path Select: Sets a quick way to choose EDO Memory read/write to improve system performance.

SDRAM RAS Latency: Set the row address of the SDRAM memory to trigger the time delay of the column address trigger.

SDRAM RAS Timing: Sets the system's row address trigger time for SDRAM memory, or refresh time.

Peer Concurrency: In order to improve the system parallelism, so that the CPU on the cache or memory or PCI devices, or PCI main signal to the PCI peripherals and so on. The higher the system intelligence, the more operations are done in parallel with the CPU, the more performance is improved.