How to Use Modelsim for pre-simulation and post-simulation? (Really oo unparalleled predecessors)

Abstract
This article describes how to use Modelsim for pre-simulation and use Quartus II and Modelsim for post-simulation.

Introduction
Use environment: US us II 8.1 + Modelsim-Altera 6.3g

Because FPGA can repeat the programming process, many developers will not use testbench. They will directly use the programmer program of Quartus II to open the Development Board, alternatively, you can use the waveform editor of us II to perform simulation. This method is feasible, but it is used for small projects. If the project is larger, quartus II is very time-consuming when fitter is used, and all over the world is using Quartus II notebook.

Compared with the proposed method, I also learned the ASIC TRICK: "Test Module first performs a forward simulation on each module, and then performs a backward simulation on each module, finally, the FPGA compaction engine is used. 』

The points of this method are:

1. testbench provides a more dynamic description grid than the waveform editor.

2. For testbench, you can use the system numbers of the Tilde, such as $ display () and $ fwrite.

However, to use testbench for simulation, you have to use Modelsim if the qaurtus II method is not available. This involves "pre-simulation" and "post-simulation 』.

The preceding "pre-simulation" is the functional simulation of Quartus II. We will not test the delay and delay of the electronic circuit, important: Check whether the optical network works in an ideal environment in accordance with the design structure [1]. Since there is no fitter segment, the speed of the mode is very fast.The result of the previous simulation is positive, but it does not indicate that the result is positive. However, if the result of the previous simulation is incorrect, the result will be incorrect..

The subsequent simulation is the timing simulation of Quartus II, which tests the delay and delay of the e-circuit, due to the fitter segment, therefore, the final result of the model is excellent. However, fitter needs to spend a lot of time in Quartus II,Therefore, the suggestion "previous simulation" is correct, and then the examination "subsequent simulation 』.

Using the waveform editor of Quartus II for pre-and post-simulation, I will no longer have more features. This article mainly describes how to use Modelsim-Altera for pre-and post-simulation.

1. Use the GUI to simulate Modelsim-Altera.

2. Use do macro to simulate on Modelsim-Altera.

3. perform post-simulation using Quartus II + Modelsim-Altera.

Counter. V/OpenGL

1 /*  
2 (C) oomusou 2008 Http://oomusou.cnblogs.com
3
4 Filename: counter. v
5 Compiler: Quartus II 8.1/Modelsim-Altera 6.3g
6 Description: simple counter
7 Release: 01/30/2009 1.0
8 */
9
10 'Timescale 1ns / 100 ps
11
12 Module Counter (
13 Input CLK,
14 Input Rst_n,
15 Output [ 3 : 0 ] CNT
16 );
17
18 Reg [ 3 : 0 ] CNT;
19 Assign CNT = CNT;
20
21 Always @( Posedge CLK, Negedge Rst_n) Begin
22 If ( ! Rst_n)
23 CNT <= # 5   4 ' H0;
24 Else
25 CNT <= # 5 CNT +   1 ' B1;
26 End
27
28 Endmodule

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A very simple counter, ranging from 0 to 15. Because Modelsim is used as the prefix, delay is implemented in Reg, but this will be automatically ignored during the synthesis of Quartus II, because delay is not a composable OpenGL.

Generally, the RTL sent to FPGA does not set the timescale. However, it is caused by the timescale parameter because it is used as a prefix of ModelSim.

Counter_tb.v/OpenGL 

1 /*  
2 (C) oomusou 2008 Http://oomusou.cnblogs.com
3
4 Filename: counter_tb.v
5 Compiler: Quartus II 8.1/Modelsim-Altera 6.3g
6 Description: simple counter testcounter
7 Release: 01/30/2009 1.0
8 */
9
10 'Timescale 1ns / 100 ps
11
12 Module Counter_tb;
13
14 Reg CLK;
15 Reg Rst_n;
16 Wire [ 3 : 0 ] CNT;
17
18 Parameter Period =   20 ;
19
20 Counter (
21 . CLK (CLK ),
22 . Rst_n (rst_n ),
23 . CNT (CNT)
24 );
25
26 Initial   Begin
27 # 0 CLK =   1 ' B0;
28 Rst_n =   1 ' B0;
29 # 5 Rst_n =   1 ' B1;
30 End
31
32 // 50 MHz
33 Always # (Period / 2 ) CLK =   ~ CLK;
34
35 Endmodule

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A typical testbench, the only thing to note is 28th rows.

Rst_n =   1 ' B0;
# 5 Rst_n =   1 ' B1;

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The reason why the rst_n must be 0 at the beginning is that Modelsim and Quartus II have different views on the reg initial value. Quartus II considers the reg initial value as 0, however, Modelsim considers reg to be an initial value of X, so it requires rst_n = 1' B0 to convert reg to 0, so that it can be confirmed only after Modelsim is used, however, Modelsim does not work like this, because Quartus II will handle it first.

However, the same testbench is used for both the frontend and backend replicas. It is recommended that the initial value of Reg be 0 with rst_n = 1' B0.

With RTL and testbench, let's take a look at how to use Modelsim as the frontend and backend imitation.

1. Use the GUI to simulate Modelsim-Altera.
ModelSim provides a full GUI. As long as you use the operation method, you can perform the previous imitation.

Step 1:
File-> new project

Step 2:
Add existing file

Add counter. V and counter_tb.v

Step 3:
Compile all

Select counter. V or counter_tb.v, press the mouse on the right side, and select compile-> compile all, then merge all the Tilde codes.

Successful renewal.

Step 4:
Simulate

On the "library" tab, select counter_tb, right-click the mouse, and select "simulate.

Simulate successful.

 

Step 5:
Add signal to wave

Add the desired receiver from objects to the wave, CLK, rst_n, and CNT.

The final result.

Step 6:
Run 300ns

The result of the last result.

2. Use do macro to simulate on Modelsim-Altera.
ModelSim also provides the macro method. All the above GUI operations can be described using TCL script.

Steps 1 and 2 are the same as before.

Step 3:
Execute macro

Counter_wave.do/Modelsim macro 

1 # Compile
2 Vlog counter . V
3 Vlog counter_tb . V
4
5 # Simulate
6 Vsim counter_tb
7
8 # Probe Signals
9 Add wave *
10
11 # 300 NS
12 Run   300 NS

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The result of the last result.

3. perform post-simulation using Quartus II + Modelsim-Altera

Step 1:
Set Quartus II to use Modelsim-Altera for post-Simulation

Assignments-> Settings-> category: EDA tool settings-> simulation: Tool Name: Modelsim-Altera
Select Run gate-level simulation automatically after compilation
Format for output netlist: OpenGL
Time Scale: 1 NS

Step 2:
Set testbench

Select compile test tables in the nativelink settings of the same region, and press testbenches .. to add counter_tb.v. Test partition name, top level module in test partition, and design instance name in test partition cannot be caught by yourself.

Step 3:
Role and Model

Processing-> Start Compilation

Download the complete program
Counter.7z

Conclusion
This article describes how to use Modelsim for pre-simulation and post-simulation. Using Modelsim can accelerate the development of FPGA and FPGA.

See also
(Original) How to Use Modelsim-Altera as the electrical model? (SOC) (Quartus II) (Modelsim)
How can I solve the problem that Quartus II cannot use Modelsim-Altera modulo? (SOC) (Quartus II) (Modelsim)
How to Implement functional simulation? (SOC) (Quartus II) (Modelsim)
(Original) How to Use Modelsim to simulate megafunction or LPM? (SOC) (volume core) (Modelsim)

Reference
[1] EDA pioneer workshop, Altera FPGA/CPLA design (Foundation), People's TV Publishing House