How to Write makefile by yourself

I believe many of my friends have had such experiences. They have looked at several pages of open-source projects.MakefileFile. In daily study and work, you can avoid it intentionally or unintentionally.Makefile, Can be changed without writing, can use IDE. ActuallyMakefileIt is not as hard to write as you think. As long as you understand the principles, you can practice it several times. You can also writeMakefileLet others look at you with envy.

Next, I will introduce my learning achievements. You are welcome to give me more corrections when you are a beginner.

To put it simply,MakefileDefines a series of rules to specify which files need to be compiled first, which files need to be compiled later, and which files need to be re-compiled, Or evenMakefile.The benefit of makefile is "automatic compilation". Once written, only one make command is required, and the entire project is fully automatically compiled, which greatly improves the efficiency of software development.

AboutProgramCompilation and link

In general, whether it is C or C ++,First, compile the source file into an intermediateCodeFile in windows, that is, the. OBJ file, and the. o file in UNIX, that is, the object file. This action is called compile ),In general, each source file should correspond to an intermediate target file (o file or OBJ file). Then merge a large number of object files into the execution file. This action is called Link ).

During compilation, the compiler requires correct syntax and correct declaration of functions and variables. For the latter, you usually need to tell the compiler where the header file is located (the header file should only be declared, and the definition should be placed in the C/C ++ file), as long as all the syntax is correct, the compiler can compile the intermediate target file.

When linking, it mainly involves linking functions and global variables. Therefore, we can use these intermediate target files (O files or OBJ files)
Link our application. The linker does not care about the source file where the function is located, but only the target file (Object
File). In most cases, because there are too many source files and too many intermediate target files are generated during compilation, You need to clearly point out the intermediate target file names during the link, which is inconvenient for compilation, we want to give
Create a package for the intermediate target file. In Windows, this package is called "library file", that is, the. Lib file. In UNIX, It is archive.
File, that is, the. A file.

Next, let's take a look at how to write makefile.

Makefile rules

Objective: Required Conditions (note that there are spaces on both sides of the colon)

Command (note that the preceding command starts with the tab key)

Explanations:

1. The target can be one or more objects, object files, execution files, or even a tag.

2. The required condition is the file or target required to generate the target.

3. The command is the script to be executed to generate the target.

To sum up, A makefile rule specifies the dependencies for compilation, that is, the target file depends on conditions, and the generation rules are described by commands.During compilation, if the file of the required condition is updated against the target, a command is generated to update the target.

The following is a simple example.If a project has three header files and eight C files, we should make the makefile look like the following in order to complete the three rules described above.

Edit: Main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o
CC-O edit main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o

Main. O: Main. c defs. h
CC-C main. c
KBD. O: KBD. c defs. H command. h
CC-c kbd. c
Command. O: Command. c defs. H command. h
CC-C command. c
Display. O: Display. c defs. h buffer. h
CC-C display. c
Insert. O: insert. c defs. h buffer. h
CC-C insert. c
Search. O: search. c defs. h buffer. h
CC-C search. c
Files. O: files. c defs. h buffer. H command. h
CC-C files. c
Utils. O: utils. c defs. h
CC-C utils. c
Clean:
Rm edit main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o

 

Write the above content to the MAKEFILE file, execute make to compile, and execute make clean to delete all target files. The final target file edit is dependent on a series of. O target files, which need to be compiled and generated using source files.

Note that there is no condition behind clean, and clean itself is not a file,It is just an action name.,If there is nothing after the colon, make will not automatically find the dependency of the file, and will not automatically execute the subsequent commands.

How make works

By default, we only enter the make command. So,

 

1. Make will find the file named "makefile" or "makefile" in the current directory.
2. If it is found, it will find the first target file (target) in the file. In the above example, it will find the file "edit, and use this file as the final target file.
3. If the edit file does not exist or is later than the edit file. O if the file modification time of the file is newer than that of the edit file, the file will be generated by executing the command defined later.
4. If. o file does not exist, so make will find the target in the current file. o file dependency. If found, it will be generated based on that rule. o file. (This is a bit like a stack process)
5. Of course, your c files and H files exist, so make will generate. o file, and then use. o The ultimate task of file life make, that is, execution file edit.

Use variables in makefile

The previous knowledge is enough for you to complete a simple makefile by yourself, but the makefile is far more subtle. Let's take a look at how to use variables in makefile.

In the above example, let's take a look at the edit rules:

 

Edit: Main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o
CC-O edit main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o

 

We can see that the strings in the [. O] file have been repeated twice. If our project needs to add a new [. O] File
So we need to add it in two places (three places, and one place in clean ). Of course, our makefile is not complex, so we are not tired of adding it in two places, but if
Makefile becomes complicated, so we may forget a place that needs to be added, leading to compilation failure. Therefore, in makefile, we
You can use variables. The makefile variable is a string, which may be better understood as a macro in C language.

So we use the variable objects

Objects =Main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o

In this way, the original makefile looks like the following:

Objects = Main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o

Edit: $ (objects)
CC-O edit $ (objects)
Main. O: Main. c defs. h
CC-C main. c
KBD. O: KBD. c defs. H command. h
CC-c kbd. c
Command. O: Command. c defs. H command. h
CC-C command. c
Display. O: Display. c defs. h buffer. h
CC-C display. c
Insert. O: insert. c defs. h buffer. h
CC-C insert. c
Search. O: search. c defs. h buffer. h
CC-C search. c
Files. O: files. c defs. h buffer. H command. h
CC-C files. c
Utils. O: utils. c defs. h
CC-C utils. c
Clean:
Rm edit $ (objects)

It seems much more convenient and easier. What if a new. o file exists? Of course, it is added in objects, so that only one change is needed, which is very convenient.

Make auto-Derivation

GNU make is very powerful. It can automatically deduce the commands behind the file and file dependency, so we do not need to go to every [. o] The files are all written with similar commands, because our make will automatically identify and deduce the commands by ourselves.

As long as make sees a [. O] file, it will automatically add the [. C] file to the dependency. If make finds
Whatever. O, then whatever. C will be the dependent file of whatever. O. And CC-C whatever. c
It will also be deduced, so our makefile no longer needs to be written so complicated. Our new makefile is released again.

Objects = Main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o

Edit: $ (objects)
CC-O edit $ (objects)

 

Main. O: defs. h
KBD. O: defs. H command. h
Command. O: defs. H command. h
Display. O: defs. h buffer. h
Insert. O: defs. h buffer. h
Search. O: defs. h buffer. h
Files. O: defs. h buffer. H command. h
Utils. O: defs. h

Clean:
Rm edit $ (objects)

Of course, if you think so manyIf the dependency between [. O] and [. H] is a bit uncomfortable,Well, there is no problem. This is very easy for make. Who calls it to provide the function of automatically deriving commands and files? Let's take a look at the latest makefile style.

Objects = Main. o kbd. O command. O display. O/
Insert. O search. O files. O utils. o

Edit: $ (objects)
CC-O edit $ (objects)

 

$ (Objects): defs. h
KBD. O command. O files. O: Command. h
Display. O insert. O search. O files. O: Buffer. h
Clean:
Rm edit $ (objects)

However, I do not recommend this method.Although simple, this method destroys the dependency of the file itself.. If there are too many files, you may not know.

How is makefile simple and powerful? In fact, makefile is far more powerful than this. Let's take a look at it later. Today we will be here first.

If you think of meArticleDon't quench your thirst. You can go here to have a look.

Finally, you are welcome to make a brick.