I. MX6 DDR parameter settings, I. mx6ddr parameter settings

I. MX6 DDR parameter settings, I. mx6ddr parameter settings
The DDR Stress Test Tool provides two purposes. First, it can be used to calibrate DDR3 to facilitate mmdc phy delay settings and PCB pairing to achieve the best DRAM performance. The entire process is fully automated, so customers can work with DDR3 in a short period of time. In addition, this tool can run a memory stress test to verify the functionality and reliability of DDR3. Stress testing can be used to verify the hardware connection, MMDC register parameters, and DDR3 mode register settings. The most important purpose of the test is to allow customers to verify that DDR3 runs stably on their own boards.
CalibrationOn the I. MX6 processor, DDR3 requires four calibration processes that fine-tune the MMDC PHY wait register correction and type the DDR3 configuration in the DDR Stress Test Tool. First, the calibration test will prompt DRAM frequency. The default values of I. MX6Q and I. MX6D are 528 MHz, and the default values of I. MX6DL, I. MX6S and I. MX6SL are 400 MHz. This is the DRAM frequency used by BSP. Press 'y' to continue the correction process. Input 'n' here will have an option to select a specific frequency. It is only used for debugging. After the DRAM frequency option is selected, the tool starts calibration.
Write Leveling Calibration
This is the first correction, used to fine-tune the delay between DRAM clock output from I. MX6 processor and write DQS, and continue the correction process by 'y. If the board has been corrected and the correction result has been integrated with the script, press 'n' to skip the correction. After you start Calibration by 'y', you need to enter the value of DDR3 Mode Register MR1. The value of MR1 can be found in the following lines of the initialization script. The value is The two highest valid bytes after The equal sign, I. e. 0x0004 on this example.
Setmem/32 0x021b001c = 0x00048031 // MMDC0_MDSCR, MR1 write, CS0The value must be the same as that in the DDR initialization script. Otherwise, The following test results will be invalid because The Value is used to restore The MR1 value of DDR3. When The write leveling mode is exited.
Read DQS Gating Calibration
The second correction process is DQS gating calibration. It is used to fine-tune the read DQS gating so that it can accurately capture the read DQS signal. The calibration program adjusts DQS gating delay to find a valid DQS delay window in the 4/256 cycle. Press 'y'/'n'
Similar intermediate operations, no translation
Calibration Results
After finishing all the calibration process, the calibration results are summarized and as shown below. The tool will proceed to run the DRAM stress test with the delay registers updated with these calibration results.
However, it is very important that these results shocould be recorded down and the DRAM initialization script shocould be updated accordingly. when porting the MMDC parameters to the firmware, the delay registers must be programmed according to the updated script. otherwise, the DDR3 may not be able to run stably on the firmware.
Generally, the procedure is as follows:References: https://community.freescale.com/docs/DOC-96412