I2S bus data communication

Source: Internet
Author: User


I2S (interic Sound Bus) is a bus standard developed by Philips for audio data transmission between digital audio devices. It uses an independent wire to transmit clock and data signals, data and clock signals are separated to avoid distortion caused by time difference. The I2S bus is simple and effective, which can effectively improve the quality of output data and is widely used in various embedded audio systems. However, in the design of the embedded audio system, not all MCU support the I2S bus format. In addition, I2S does not have a unified interface standard, and equipment interfaces produced by different manufacturers are also varied, the implementation of I2S bus through software simulation can effectively solve the problems that occur when the MCU and the device are not supported to implement data transmission through I2S bus.

In this paper, the I2S bus is simulated in the Ethernet digital voice broadcast system to realize voice data transmission.

 1 I2S bus specification

I2S is a three-line bus with three signals:

① Serial clock sck, also known as bck ). That is, each time one digital audio data is sent, the sck has one pulse. Sck frequency = 2 × sampling frequency × number of sampling digits. During data transmission, both the transmitter and receiver of the I2S bus can be used as the host of the system to provide the clock frequency of the system.

② Frame clock WS, that is, the command (Channel) selection, used to switch the data of the left and right channels. The Ws frequency is equal to the sampling frequency, which is provided by the system host. If ws is set to "1", the data in the left channel is transmitted. if ws is set to "0", the data in the right channel is transmitted.

③ Serial data signal SD, used to transmit audio data in binary complement representation.

No matter how many bits are valid, the highest bit (MSB) of the data bit is always transmitted first. The number of valid bits that can be sent once is determined by the number of bits in I2S format.

1 Typical I2S Signal Time Series 1 shows

Figure 1 typical sequence of I2S Bus

With the development of technology, a variety of different data formats have emerged under the unified I2S interface. Based on the difference between SD signals and sck and WS, SD signals are divided into two formats: Left-aligned and right-aligned, as shown in figure 2 and Figure 3.

Figure 2 left-aligned format of 16-bit valid digits

Figure 3 right alignment of 16-bit valid digits

In the preceding two data transmission formats, when WS is set to "1", the left-channel data is transmitted. When WS is set to "0", the right-channel data is transmitted. To ensure the correct transmission of digital audio signals, the sender and receiver must adopt the same data format.

  2 software simulation I2S

An Ethernet digital voice broadcast system is a broadcast system that provides audio services for communication media over Ethernet. It transmits voice signals over Ethernet in the form of a standard IP packet to implement the voice broadcast function. The system collects voice data from a microphone on a PC and sends the collected voice data to an embedded terminal over Ethernet, the embedded terminal converts the received voice data to a number or mode for playback. The system implementation diagram 4 is shown in [5].

Figure 4 Diagram of the Ethernet Digital Speech broadcast system

Figure 5
Link between lm3s8962 and ms6336

The MCU lm3s8962 of the broadcast system terminal sends the received voice data to the speech decoding chip ms6336 through the I2S bus for data/mode conversion and playback,

Figure 5 shows the connection between lm3s8962 and ms6336. In order to completely restore the voice signal, it is necessary to ensure that the software simulated I2S signal timing is strictly accurate, and the high and low level conversion is implemented using a delay program. Ms6336 is a 16-bit D/A chip, as shown in the I2S timing 6.

Figure 6 typical I2S sequence diagram of ms6336

The voice data in the system is dual-channel, with 16-bit sampling. The data at one sampling point is 4 bytes, and the data at one sampling point is sent to ms6336 by MCU. The data transmission process is shown in Step 7.

Figure 7 data transmission process of one sampling point

The software simulation I2S pin is defined as follows:

# Define i2s_ws gpio_pin_5 // select the clock control bit for simulating I2S Channels

# Define i2s_bck gpio_pin_6 // simulate the I2S-Bit Clock Control bit

# Define i2s_data gpio_pin_7 // simulate I2S data transfer bit

The steps for simulating the I2S bus are as follows:

① The sck value and the WS value are calculated based on the speech data sampling rate and the number of sampling digits (the WS value is equal to the sampling frequency ).

If the system sampling rate is 44.1 kHz, sck = 2 × 44.1 kHz × 103 × 16 = 1 411 200Hz, Ws = 44 100Hz. 1 sck clock cycle T = 1/sck = 07 μs. To use a latency program to simulate sck clock cycles, you need to apply an oscilloscope to precisely delay time. The latency of one sck cycle in the system is delayi2s (2 ).

② Set WS, BCK, and data to a high level.

③ Select the Left and Right audio channels. First, send left-channel data, and set ws to low (if the right-channel data is sent, set ws to high ).

For (channelcnt = 0; channelcnt <2; channelcnt ++) {// select two-channel playback

If (channelcnt = 0) {// select high for the right channel

Hwreg (gpio_porta_base + (gpio_o_data + (i2s_ws <2) = ~ I2s_ws;


Else {// select the signal as low level for the left channel

Hwreg (gpio_porta_base + (gpio_o_data + (i2s_ws <2) = i2s_ws;




④ Select High and Low bytes. The left-side channel data is sent in the order of high and low bytes. A periodic serial clock is sent before the High-byte 1st-bit data is sent.

For (horlcnt = 0; horlcnt <2; horlcnt ++) {// audio channel data high/low bytes Selection

If (channelcnt = 1) {// left channel

If (horlcnt = 0) {// low byte

C = * (sampledata + 1); // sampledata points to the first address of the audio data buffer, that is, the left audio channel low byte.

Delayi2s (2); // before sending the first data bit, a one-bit clock cycle needs to be delayed.


Else {// low byte

C = * sampledata;





⑤ Start to transmit audio data (the audio data is transmitted at the sck descent edge to prepare the data, and the rising edge of sck is sent.

To the data receiver ). Send the highest byte of the left-channel data of the sampling point to SD and set sck to a low level. At this time, it is the descent edge of sck and the data is ready. After half a sck period, the sck is set to a high level. In this case, the data on the SD line is sent to the data receiver, and the sck period is delayed. In turn, the left-channel residual BIT data is sent in the highest bit mode.

For (bitcnt = 0; bitcnt <8; bitcnt ++) {// The length of data transmitted once is 8 bits, transmit the high byte before transmitting the low byte, set the clock line sck to low, and start preparing the data bit.

Hwreg (gpio_porta_base + (gpio_o_data + (i2s_bck <2) = ~ I2s_bck;

If (C <bitcnt) & 0x80 ){

Hwreg (gpio_porta_base + (gpio_o_data + (i2s_data <2) = i2s_data;


Else {

Hwreg (gpio_porta_base + (gpio_o_data + (i2s_data <2) = ~ I2s_data;


Delayi2s (1); // sets the time interval of half a sck to a high value and starts data bit transmission.

Hwreg (gpio_porta_base + (gpio_o_data + (i2s_bck <2) = i2s_bck;

Delayi2s (1); // delay: Half a clock cycle


6. After sending data from the left channel of one sampling point, two sck cycles are delayed and data from the right channel is sent (the process of sending data from the same left channel ).

According to the above process, the data of each sampling point can be processed, and audio data can be transmitted through the software simulation I2S bus. The above implementation is a typical I2S time series simulation, while the left and right alignment formats only differ slightly in time series. The simulation implementation process is basically the same as the typical I2S bus simulation implementation process.


The Application of Software Simulation in the Ethernet digital voice broadcast system to implement the I2S bus time sequence can successfully realize the data transmission of voice signals and real-time broadcast of voice signals, it indicates the feasibility of software simulation to implement I2S bus, and provides a feasible method for communication between MCU and various I2S bus devices that do not support I2S bus. However, when the application software simulates the real-time playback of voice signals in the I2S Ethernet digital voice broadcast system, there is some noise, indicating that there is a lack of accuracy in the implementation of I2S timing using software simulation.

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