I2S Audio bus Learning (iv) I2S Interface Design

I2S Audio bus Learning (iv) I2S interface design I. Data Transmission Design 1 sending end As ws signal changes, a WSP pulse signal is exported, and data left or data right is loaded into the parallel shift register to activate the output data. Serial Data is removed along the clock descent. The default input value of serial data is 0, so all data after the LSB is set to 0.

2. Design Diagram 2 of the Data receiving endAs the first ws signal changes, WSP resets the counter along the descent of the sck signal. After the "1 out of N" decoder decodes counter values, the first serial data (MSB) is stored in B1 on the rising edge of the sck clock signal. As the counter grows, the subsequent data is stored in B2. When the next ws signal changes, the data is stored in the left (Channel) or right (Channel) latches based on the changes in the WSP pulse, in addition, the b2-bn data is cleared and the counter is reset. If redundant data exists, the data after the percentile is ignored. Note: The decoder and counter (in the dotted line) can be replaced by an N-bit shift register, as shown in 3.
When the count is full, that is, when the ENN is high, the calculator en signal becomes low, so that the counter stops counting and the serial and conversion module stops receiving data.Figure 3 receiving end