IA-64Linux Storage Management

Article title: IA-64Linux storage management. Linux is a technology channel of the IT lab in China. Includes basic categories such as desktop applications, Linux system management, kernel research, embedded systems, and open source.
The Android processor using the explicit parallel command computing (EPIC) structure is Intel's next-generation 64-bit processor. many large companies, such as HP, SGI, and Intel, have launched high-performance Android server systems. Linux is currently one of the mainstream operating systems that support the IA-64 server platform. This paper focuses on the IA-64 Linux storage management, including IA-64 Linux flexible address space division, page table, TLB and other mechanisms.
　　
　　 Introduction
Intel's IA-64 architecture is a cost-effective, scalable, and superior performance 64-bit computing platform. From the technical point of view, unlike the general processor using excessive amount of technology, the main characteristic of the IA-64 architecture is the use of EPIC structure. The EPIC structure uses the compiler to mine the application's command-level concurrency, and uses the generated machine language to explicitly guide the hardware execution program, reducing the complexity of the processor hardware, the compilation software is used to mine more and more parallel commands within a wider scope. the EPIC architecture represents the new idea of the current processor design.
　　
Intel has successfully launched the Anteng and Anteng 2 processors. The performance of the Anteng 2 processor in the SPECfp2000 test is very outstanding. it only lags slightly behind Alpha21364 in the SPECfp2000 Peak test, in the SPECfp2000 Base test, the top spot was the top spot. At the same time, Intel focused heavily on the development of IA-64 architecture operating systems, as early as 1999, Intel joined HP, SGI, RedHat, VA Linux and IBM to launch Intel IA-64's Trillian project, this project is designed to achieve Linux porting and optimization in the IA-64 platform, many members contribute to this project, such as HP completed the kernel, IBM completed performance analysis tools and evaluation, intel completes kernel and EFI (Extensible Firmware Interface), RedHat completes GNUPRO development tools, and SGI Completes compiler and kdb. At present, Red Hat, TurboLinux, Caldera and SuSe have released a Linux version that supports the IA-64 architecture, Linux has become an important operating system to support the IA-64 architecture, HP's David Mosberger program for maintaining and managing IA-64 Linux has been integrated into Linux kernel versions.
　　
　　 Second IA-64 Linux address space Division
From the user's perspective, the virtual address of a Linux process is linear. it consists of two parts: kernel space and user space. The user space occupies the lower part of the address, from 0 to TASK_SIZE (the TASK_SIZE value is related to the specific hardware platform, in include/asm/processor. h), and the rest is the kernel space. The user space is private to the process. The address is maintained and managed by the page table of the process. The kernel space is shared by all processes. When running in the user mode, only the user space can be accessed. the read, write, and execution of the kernel space will lead to protection conflict faults, this prevents errors or malicious user code from damaging the kernel. when running in kernel mode, users and kernel space can be accessed.
　　
The IA-64 architecture supports 64-bit virtual address space, which divides 64-bit virtual address space into 8 equal zones, each with 2048 P bytes, use the 3-digit (61-63) height of the virtual address to represent the area code. 1.
　　
　　　
　　
IA-64 virtual address space
　　
Currently, the application's demand for virtual addresses has not reached the full 64-bit level. Therefore, full 64-bit virtual addresses are not required for implementation. the IMPL_VA_MSB constant is used to determine the unimplemented virtual address space range, its value can be between 50-60, and IMPL_VA_MSB + 1 to 60 is the unimplemented virtual address bit. The unimplemented address bit is extended by the low address bit of the virtual address, if the IMPL_VA_MSB value is less than 60, the extension divides the virtual address space in a zone into two parts, the unimplemented part is in the middle, as shown in 2 (IMPL_VA_MSB = 50 ). Unauthorized access is not allowed. if the access is in the user state, an invalid command error is generated. if the access is in the core state, the operating system kernel crashes.
　　
　　　
　　
Linux/IA-64 User space size is still defined by the TASK_SIZE constant, using zone 0-4 as the user space in the IA-64, Zone 5-7 as the core space, PAGE_OFFSET constant pointing to zone 7th, 3. The kernel space can be further divided into page table ing segments and peer-to-peer ing segments. The page table ing segment is mapped by the kernel page table and is mainly used to implement the vmalloc region of the kernel. the kernel uses the vmalloc region to implement continuous allocation of large memory blocks with virtual addresses, the address range of this region is determined by VMALLOC_START and VMALLOC_END. The peer-to-peer ing segment contains the Linux kernel, such as the kernel body segment, data segment, and stack segment. Peer-to-peer ING is very special. the virtual address of this segment can be mapped directly to the physical address. the ing formula is very simple. Generally, the virtual address is directly subtracted from a base address (for example, PAGE_OFFSET) the physical address is obtained.
　　
　　　
　　
Figure 3 IA-64 Linux address space Division
　　
In the core space, zone 7 implements equal-to-peer Cache ING of the Cache, zone 6 implements non-Cache equal-to-peer ing, and Zone 5 implements the kernel page table ing segments. The first page in area 5 is called the guard page, which is not mapped. any access to this page will cause a page fault, this page is used for quick permission check when copying data in the user space and core space. The second page is called the gate page, which is used to support conversion at the core and user level. The third page is called the per-CPU page. It provides the local information of each CPU for multi-processor systems. The remaining part of area 5 is used in vmalloc, from VMALLOC_START to VMALLOC_END. The features of each region in Linux/IA-64 are shown in the following table,
　　
Area code uses page size range ing
7Cache256MB global peering
6 Non-Cache256MB global peering
5 vmalloc, guard, 8 K global page table
4. 8 K process page table of stack segments
3 Data Segment 8 K process page table
2. 8 K process page table
1 Shared Memory 8 K process page table
0IA-32 simulate 8K process page table
　　
Linux/IA-64 based on the partition address space and the traditional X86 architecture is different, has the following advantages: (1) can make full use of the IA-64 to provide support for a variety of physical page size characteristics, the partition code is used to implement different page sizes, for example, the operating system kernel code and data are in zone 7. the page size is 256 MB, and the user process body segment is in Zone 2, the 8 kB page is used to effectively save system hardware resources and improve system performance. (2) facilitate application expansion. The text segment, data segment, and stack segment of the user process are in different zones, and the difference between each zone is 2048 P bytes. Therefore, the expansion of the text segment or data segment will not cause overlapping addresses between sections. (3) facilitates zone-based sharing and protection.
　　
　　 Three-page table
IA-64 Linux maintains a page table for each process in physical memory and accesses the page table through the peer-to-peer ing kernel segment in zone 7th. Page tables reside in the memory and cannot be switched to the disk. This simplifies the kernel design, because the kernel does not need to consider Nested page faults. Currently, mainstream hardware platforms do not support variable page sizes. for example, X86 only supports two page sizes: 4 KB or 4 MB (If PAE is supported, there are 2 MB ), the IA-64 supports 4 kB, 8 kB, 16 KB, 64 KB, 256KB, 1 MB, 4 MB, 16 MB, 64 MB, and 256 MB page size, so the page mechanism is more flexible and convenient. At present, IA-64 Linux still uses three levels of page table tree structure, each page frame 8 kB, each level of directory occupies a page box, each 8 bytes size, by the global directory (PGD), the middle Directory (PMD) and page table items (PTE. The IA-64 Linux User space virtual address format is
　　
　　　
　　
Figure 4 user space virtual address format (8 KB page)
　　
The global directory index is divided into pgdh (3 bits) and pgdl (7 bits). The global directory index is divided into two parts and can be mapped to each partition through the high 3 bits of the virtual address, ar. the k7 register points to the base address of the page table tree of the current process. 5th to 7th is reserved for the kernel, the user process is not allowed to map any address pgdh greater than 5 to the user space, IA-64 Linux by setting FIRST_USER_PGD_NR to 0, USER_PTRS_PER_PGD is 640 to achieve, therefore, 3/8 (Zone 5, Zone 6, and Zone 7) address space is useless in the Global Directory of the process page table.
　　
　　　
　　
Figure 5 page table ing kernel segment virtual address format (8 KB page)
　　
The kernel uses an independent page table to manage the page table ing kernel segments. different from a page table of each process in the user space, the page table belongs to the entire kernel and has nothing to do with the currently running process. IA-64 Linux uses zone 5th to implement page table ing kernel segments. The fixed value from 61 to 63 is 5, and the global directory ranges from 33 to 42. it is continuous instead of being divided into two parts like the user's virtual address space page table.
　　
IA-64 page table items support short and long modes. In short mode, each page table item has 8 bytes. it is a linear page table. in Short mode, you can use a self- ing page table. In the long mode, each page table item contains 32 bytes. it is a Hash page table. the Hash function is embedded in hardware. The Long mode supports word protection and multiple page sizes in the same domain. Linux page tables adopt the Short mode, which makes it easy to combine Linux page tables with VHPT walker. in the long mode, different protected words can be specified for each page table item, so TLB is more efficient, however, using the long mode requires extra memory space and conversion to ensure the Cache consistency of the page table.
　　
　　 Four TLB
Linux/IA-64 virtual/virtual address transformation by IA-64 TLB (Translation Lookaside Buffer) mechanism and Linux virtual memory management collaborative work, efficient virtual/virtual address transformation can greatly improve the performance of Linux. Logically, IA 64 TLB can be divided into ITLB of commands and DTLB of data. ITLB can be divided into ITC and ITR, and DTLB can be divided into DTC and DTR ,.
　　
　　　
　　
Fig 6 IA-64 TLB tissue
　　
The difference between TC (Translation Cache) and TR (Translation Register) is that the replacement policy is different. TC replacement policy is controlled by hardware, while TR replacement policy is specified by software, therefore, TR has the following features: after the software inserts a ing in TR, the ING remains valid unless the software inserts a new ing or clears the ING. Linux/IA-64 with TR to complete the key address transformation, ensure that the access to the key address memory can hit TLB, reduce the number of TLB failure. Due to the limited TR resources in the processor, Linux/IA-64 uses a large page (256 MB), through the TR Register to map the kernel code and data in Area 7, through peer-to-peer ING to quickly complete the virtual and virtual address transformation, the current IA-64 Linux ITR0 ing Linux kernel code, DTR0 ing kernel read-only data, ITR1 ing EFI (Extensible Firmware Interface) required PALcode, DTR1 maps data of each CPU, and DTR2 maps data to the kernel stack.
　　
In addition to the basic TLB functionality, the IA-64 architecture also provides zone (region) registers, protection key registers, and VHPT (Virtual Hash Page Table) three hardware structures of walker accelerate virtual/virtual address transformation. Figure 7