ICPs design frontend-to-backend processes and EDA tools.

The distinction between the IC front-end design (logical design) and the backend design (Physical Design): whether the design is related to the process or not, the result of the front-end design is the gate-level network Table circuit of the chip.

The front-end design process and EDA tools are as follows:

1. Architecture Design and verification: divide the overall design modules as required.

For architecture model simulation, you can use Synopsys's cocentric software, which is a simulation tool based on system C.

2. HDL design input: The design input methods include: HDL language (OpenGL or VHDL) input, circuit diagram input, and state transition diagram input.

The tools used include active-HDL, And the RTL analysis and check tool includes the Leda of Synopsys.

3. Pre-simulation tool (functional simulation): preliminary verification of whether the design meets the specifications.

The tools used include: VCs of Synopsys, Modelsim of mentor, OpenGL-XL of cadence, and NC-Tilde of cadence.

4. logical synthesis: Convert the HDL language into a gate-level network Table netlist. You need to set constraints for integration, that is, the labels that you want to integrate the circuit on the target parameters such as area and time series.

Accurate; logical synthesis requires specifying a database based on which different comprehensive databases are used, which may vary in time series and area. The simulation before logical synthesis is the former simulation, and the latter is the latter simulation.

The tools used include: Design Compiler of Synopsys, PKS of cadence, and Synplify of synplicity.

5. Static Time Series Analysis Tool (STA): in time series, check the setuptime and hold time of the circuit for any violation ).

The tool used is Synopsys's prime time.

6. form verification tool: verifies the integrated network table in terms of functions. The equivalence check (equivalence check) method is commonly used, and the HDL design after function verification is used as the parameter.

Test whether the functions of the integrated network table are equivalent. This is done to ensure that the circuit function described in the original HDL is not changed in the logical synthesis process.

Tools used: formality of Synopsys

1. Data preparation. For CDN's Silicon Ensemble, the data required for backend design mainly includes:

The Foundry factory provides standard unit, macro unit and I/O pad library files, which include physical library, time series library and network Table Library

In the form of. Lef,. TLF, And. v. The front-end chip design is integrated to generate a door-level network table

Script file for time series constraints and clock definitions, the generated. GCF constraint file, and Def (Desi) for defining the power pad.

GN exchange format) file. (For Astro of Synopsys, the door-level network table generated after synthesis,

The time series constraint file SDC is the same. The pad definition file-TDF,. TF file-technology file,

The Foundry factory provides standard unit, macro unit, and I/O pad library files with fram, cell view, lm View

Format (milkway reference library and DB, lib file)

2. Layout Planning. Mainly standard unit, I/O pad and macro unit layout. I/OPAD provides a bit in advance

The macro unit is placed according to the time sequence requirements, and the standard unit is given a certain area automatically placed by the tool

. After the layout planning, the chip size, core area, row form, power supply and ground ring and strip are determined.

Come down. If it is necessary to automatically place the standard unit and macro unit, you can first make a PNA (Power netw

Ork analysis) -- IR drop and em.

3. Placement-automatic placement of standard units. Position and placement of macro unit and I/O pad after Layout Planning

The region of the standard unit is determined. The information Se (Silicon Ensemble) is passed to the PC (pH

Ysical compiler), the PC automatically places tags based on the network table and time series constraints obtained from the comprehensive. DB file.

Quasi-unit, Timing Check and unit Placement Optimization at the same time. If you are using PC + Astro

Then you can use write_milkway and read_milkway to pass data.

4. Clock Tree Generation (CTS Clock Tree Synthesis ). The clock network in the chip needs to drive in the circuit

Some time series units, so the clock source terminal unit carries a lot of loads, the load delay is very large and unbalanced, need to insert slow

Reduce load and balance latency. The clock Network and Its buffers constitute the Clock Tree. It usually takes several times to complete.

To make an ideal Clock Tree. --- Clock skew.

5. Stas static timing analysis and post-simulation. After the Clock Tree is inserted, the position of each unit is determined,

The tool can propose the connection parasitic parameters in the form of global route. At this time, the extraction of the delay parameters is more accurate.

Se transmits the. V and. SDF files to primetime for static timing analysis. After confirming that there are no time series violations

The parts are delivered to the front-end personnel for post-simulation. For Astro, after detail routing, use the starrc XT Parameter

Number extraction. The generated e. V and. SDF files are passed to primetime for static timing analysis, which will be more accurate.

6. ECO (engineering change order ). For problems in static timing analysis and post-simulation,

Make small changes to the circuit and unit layout.

7. Insert filler (padfliier, cell filler ). Filler refers to the standard unit library and I/O P

Logical-independent padding defined in the ad library, used to fill the gap between the standard unit and the standard unit, I/O pad and I/O P

The gap between ad is mainly to connect the diffusion layer to meet DRC rules and design requirements.

8. routing ). Global route -- trackassign -- detail routing -- Routing

Optimization cabling refers to the deployment

Under the conditions of insulated electrical performance constraints, each unit and I/O pad are connected by a Interconnect Link based on the connection relationship of the circuit.

These are performed under the timing drive (timing driven) condition to ensure the connection length of key time series paths.

Minimum. -- Timing report clear

9. Increase in dummy metal. Foundry plants all have requirements on metal density so that the metal density is not low.

To prevent over-etching of the metal layer in the chip manufacturing process to reduce the circuit

Performance. Dummy metal is added to increase the density of the metal.

10. DRC and LVS. DRC is a design rule inspection (spacing,

Width), it also includes antenna effect check to ensure that the chip is normal. LVS mainly displays the layout and the network.

To ensure that the layout circuit of the stream chip is consistent with the actual required circuit. Check DRC and LVS-EDA tools

. Astro also include LVS/DRC performed by synopsy Hercules/mentor calibre/CDN Dracula

Check commands.

11. tape out. Upload the final gds ii file when all checks and verifications are correct

Delivered to foundry plant for mask Manufacturing