(iii) Memory SDRAM Drive Experiment

Source: Internet
Author: User

SDRAM Chip Explanation:

Address: Line Address (A0-A12) column address (A0-A8) chip selection signal (BA0 BA1) (L-bank) (because SDRAM has 4 pieces)

The only difference between the two SDRAM connections is the UDQM LDQM

DQM0---tablets 1 ldqm

DQM1----Tablets 1 UDQM

DQM2----Tablets 2 LDQM

DQM3---tablets 2 udqm


1, read operation (see Yang Ji 121)

Address line to send on the address of the data to read the natural address to do, (just like delivery, first you have to determine the destination address to be served where the same)

Confirm Address: CS Low level is nSCS0 pull low, select the foreign connection equipment, L-bank also selected SDRAM internal corresponding to a piece (so address), and at the same time

RAS line Address Select the communication number is also in a valid state, of course, this is to write column address must be line address stability only line (need time trcd=2),

The column address also pretends to be unstable, requiring a time delay (what we call the CAS incubation period), of course not unstable, is the chip itself.

Address such a step-by-step determination, you can read (how not to write Ah, because WE are invalid, not to write Ah, so the equivalent of reading. Valid, is written)

2. Pre-charge operation

To address another line of the same l-bank, you naturally turn off the original line. Re-release the column address.

Turn off the original line to pre-charge (to overwrite the entire memory and then close the action line)

That is, the pre-charge contains two steps (rewrite + close the original line), but the pre-charge is not periodic, only in the read operation execution

3. Write operation

As with the read operation, the only difference is that after the line delay (TRCD) The input write command (we low active, pull down, can write)

After the last data is written, delay the TWR and send the pre-charge command. Close the activation page.

The next operation can be done after the TRP time has been waited.

4. Write operation

5. Refresh operation


The above can be combined with Yang Ji books and s3c2440 chip manual memory Contrl to analyze, not difficult, in addition to refresh no patience to see, fortunately


Start a memory-driven experiment: (2.6.8)

(iii) Memory SDRAM Drive Experiment

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