Linux implementation of ISA bus DMA-Linux Enterprise Application-Linux server application information. The following is a detailed description. Keywords: Linux, I/O, ISA bus, Device Driver
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DMA is a hardware mechanism that allows two-way (to device or from device) data transmission between peripherals and system RAM without the involvement of the CPU. Using DMA can remove the system CPU from the actual I/O data transmission process, thus greatly improving the system throughput (throughput ).
Because DMA is a hardware mechanism, it is usually related to the hardware architecture, especially the peripheral bus technology. For example, the DMA mechanism of the ISA card is different from that of the PCI Card. This site mainly discusses the DMA technology of ISA bus.
1. DMA Overview
DMA is a data transmission mechanism between peripherals and primary storage. Generally, there are two data transmission methods between peripherals and primary storage: (1) Pragrammed I/O (PIO) method, that is, the CPU continuously reads and writes the memory units (8-bit, 16-bit, or 32-bit) of the peripherals through memory read/write commands or I/O commands until the entire data transmission process is completed. (2) The DMA Controller (DMAC) completes the entire data transmission process. During this period, the CPU can execute other tasks concurrently. After the DMA ends, DMAC notifies the CPU that data transmission has ended through interruption, and then the CPU executes the corresponding ISR for post-processing.
When DMA technology was developed, ISA bus became popular in PCs. Therefore, the DMA data transmission of the ISA card is achieved by controlling two cascade 8237 DMAC in the ISA bus. This type of DMA mechanism is also called "standard DMA" (standard DMA ). Standard DMA is also known as "third-party DMA", because the system DMAC completes the actual transmission process, therefore, it is a "third party" relative to the "first two Parties" of the transmission process (the sender and receiver of the transmission ".
The standard DMA technology has two main disadvantages: (1) the data transmission speed of 8237 DMAC is too slow and cannot be used with a higher-speed bus (such as PCI. (2) Two 8237 DMAC instances provide only eight DMA channels, which also becomes the bottleneck limiting the increase of system I/O throughput.
For the above two reasons, the PCI Bus architecture design is a DMA mechanism that becomes the first-party DMA, also known as "Bus Mastering ). In this case, the PCI Card for transmission must obtain the master control right of the system bus before data transmission. The actual transmission is not implemented by using the slow isa dmac, but by the DMA circuit embedded in the PCI Card (faster than the traditional isa dmac. Bus Mastering DMA allows PCI peripherals to get the desired transmission bandwidth, so it meets the requirements of modern high-performance peripherals than standard DMA functions.
With the continuous development of computer peripheral technology, modern Ultra DMA (UDMA), which can provide faster transmission rates, has also been widely used. In the subsequent sections, we will only discuss the implementation of the standard DMA technology of ISA bus in Linux. Remember: The ISA card uses almost no DMA in the Bus Mastering mode, while the PCI card uses only the DMA in the Bus Mastering mode, and never uses the standard DMA.
2. Intel 8237 DMAC
In the original ibm pc/XT, there was only one 8237 DMAC, which provided four 8-bit DMA channels (DMA channel 0-3 ). An additional 8237 DMAC (4 16-bit DMA channels, 4-7 DMA channels) was added from ibm ). Two 8237 DMAC instances provide 8 DMA channels for the system. In contrast to the Cascade Method of Interrupt Controller 8259, the first DMAC is cascade to the second DMAC, and channel 4 is used for DMAC cascade, so it is unavailable for peripherals. The first DMAC is also called "slave DAMC", and the second DMAC is also called "Master DMAC ".
Next we will describe the DMAC structure of Intel 8237 in detail.
Each 8237 DMAC provides four DMA channels, each of which has its own registers, and 8237 itself also has a set of control registers to control all the DMA channels it provides.
2.1 DMA channel register
8237 each DMA channel in DMAC has five registers: Current address register, current count register, address register (also known as offset register), Count register, and page register. The first two internal registers are 8237, which are invisible to the outside.
(1) Current Address Register: Each DMA channel has a 16-bit Current Address Register, indicating a DMA Transfer Transaction (Transfer Transaction) the address of the DMA physical memory for the current DMA transfer operation. Before each DMA transfer starts, 8237 will automatically use the value in Address Register of the channel to initialize this Register; the value of this register is automatically increased or decreased after each DMA transfer operation during the transfer transaction.
(2) Current Count Register (Current Count Register): Each DMA channel has a 16-bit Current Count Register, indicating the amount of untransmitted data in the Current DMA transfer transaction. Before each DMA transfer transaction starts, 8237 will automatically use the value in the Count Register of this channel to initialize this Register. The value of this register is automatically increased or decreased after each DMA transfer operation during the transfer transaction (step 1 ).
(3) Address Register or Offset Register: Each DMA channel has a 16-bit Address Register, the offset of the start position of the dma buffer in system ram on the page.
(4) Count Register: Each DMA channel has a 16-bit Count Register, indicating the size of the DMA buffer.
(5) Page Register: This Register defines the base address of the physical Page where the starting position of the DMA buffer is located, that is, the Page number. The page register is similar to the segment base register in the PC.
2.2 8237 control register of DAMC
(1) Command Register)
This 8-bit register is used to control the operations on the 8237 chip. Their definitions are shown in:
(2) Mode Register)
It is used to control the transmission modes of each DMA channel, as shown below:
(3) Request Register)
Used to send DMA requests to each DMA channel. Your definitions are as follows:
(4) Mask Register (Mask Register)
Used to shield a DMA channel. When a DMA channel is blocked, it cannot serve the DMA request until the channel shield code is cleared. Your definitions are as follows:
The preceding shielded Register is also known as the Single Channel Mask Register because it can shield only one Channel at a time. In addition, there is a shielding register, which can shield all four DMA channels at a time, as shown below:
(5) Status Register)
A read-only 8-bit Register indicates the current status of each DMA channel. For example, whether the DMA channel is serving a DMA request or whether the DMA transmission transaction on a DMA channel has been completed. Your definitions are as follows:
2.3 dmac I/O port address
The registers of the master and slave DMAC are all located in the I/O port space. In addition, some I/O port addresses have different meanings for I/O read and write operations. As follows:
Slave DMAC's I/O port Master DMAC 'sI/O port read write
Address Register of 0x000 0x0c0 Channel 0/4
0x001 0x0c1 Channel 0/4 Count Register
Address Register of 0x002 0x0c2 Channel 1/5
0x003 0x0c3 Channel 1/5 Count Register
Address Register of 0x004 0x0c4 Channel 2/6
0x005 0x0c5 Channel 2/6 Count Register
Address Register of 0x006 0x0c6 Channel 3/7
0x007 0x0c7 Channel 3/7 Count Register
0x008 0x0d0 Status Register Command Register
0x009 0x0d2 Request Register
0x00a 0x0d4 Single Channel Mask Register
0x00b 0x0d6 Mode Register
0x00c 0x0d8 Clear Flip-Flop Register
0x00d 0x0da Temporary Register Reset DMA controller
0x00e 0x0dc Reset all channel masks
0x00f 0x0de all-channels Mask Register
The addresses of Page Register of each DMA channel in the I/O port space are as follows:
DMA channel Page Register 'si/O port address
0 0x087
1 0x083
2 0x081
3 0x082
4 0x08f
5 0x08b
6 0x089
7 0x08a
Note:
1. the Address Register of each DMA channel is a 16-bit Register, but its corresponding I/O port is 8-bit wide, therefore, two consecutive I/O port read/write operations are required for reading and writing this register. The low 8 bits are first sent, and then the high 8 bits are sent.
2. count Register of each DMA channel: this is also a 16-Bit Width Register (whether for 8-bit DMA or 16-bit DMA), but the corresponding I/O port is also 8-Bit Width, therefore, reading and writing this register also requires two consecutive I/O port read and write operations. In addition, it also sends an 8-bit low and then an 8-bit high. The value written to this register should be the value after the length of the data to be transferred minus 1. During the DMA transfer transaction, the value in this register is reduced by 1 after each DMA transfer operation, therefore, the value obtained by reading this register will be the value after the length of the remaining untransmitted data in the current DMA transaction is reduced by 1. When the DMA transfer transaction ends, the value in this register should be set to 0.
2.4 typical use of DMA Channels
In a typical PC, some DMA channels are usually used for standard peripherals in some PCs, as shown below:
Channel Size Usage
0 8-bit Memory Refresh
1 8-bit Free
2 8-bit Floppy Disk Controller
3 8-bit Free
4 16-bit Cascading
5 16-bit Free
6 16-bit Free
7 16-bit Free
2.5 start a DMA transfer transaction
To start a DMA transfer transaction, you must program 8237. The typical steps are as follows:
1. Use CLI commands to disable interruption.
2. Disable the DMA channel that will be used for this DMA transfer transaction.
3. Write 0 to the Flip-Flop register to reset it.
4. Set Mode Register.
5. Set Page Register.
6. Set Address Register.
7. Set Count Register.
8. Enable the DMA channel that will be used for the DMA transfer transaction.
9. Use the STI command to enable interruption.
3 Linux 8237 DMAC for read/write operations
Because the registers of DMAC are configured in the I/O port space, reading and writing 8237 DMAC is platform-related. For x86 platforms, Linux implements read and write operations on two 8237 DMAC instances in the include/asm-i386/Dma. h header file.
Macro definition of port address and register value 3.1
In Linux, the macro MAX_DMA_CHANNELS is used to indicate the number of current DMA channels of the system, as shown below:
# Define MAX_DMA_CHANNELS 8
Then, the macro IO_DMA1_BASE and IO_DMA2_BASE are used to represent the port base addresses of the two DMAC ports in the I/O port space respectively:
# Define IO_DMA1_BASE 0x00
/* 8 bit slave DMA, channels 0 .. 3 */
# Define IO_DMA2_BASE 0xC0
/* 16 bit master DMA, ch 4 (= slave input) .. 7 */
Next, Linux defines the port addresses of various DMAC control registers. The port addresses of each control register of slave SMAC are defined as follows:
# Define dma1_1__reg 0x08/* command register (w )*/
# Define DMA1_STAT_REG 0x08/* status register (r )*/
# Define DMA1_REQ_REG 0x09/* request register (w )*/
# Define DMA1_MASK_REG 0x0A/* single-channel mask (w )*/
# Define DMA1_MODE_REG 0x0B/* mode register (w )*/
# Define DMA1_CLEAR_FF_REG 0x0C/* clear pointer flip-flop (w )*/
# Define DMA1_TEMP_REG 0x0D/* Temporary Register (r )*/
# Define DMA1_RESET_REG 0x0D/* Master Clear (w )*/
# Define DMA1_CLR_MASK_REG 0x0E/* Clear Mask */
# Define DMA1_MASK_ALL_REG 0x0F/* all-channels mask (w )*/
The port addresses of control registers of Master DMAC are defined as follows:
# Define dma2_1__reg 0xD0/* command register (w )*/
# Define DMA2_STAT_REG 0xD0/* status register (r )*/
# Define DMA2_REQ_REG 0xD2/* request register (w )*/
# Define DMA2_MASK_REG 0xD4/* single-channel mask (w )*/
# Define DMA2_MODE_REG 0xD6/* mode register (w )*/
# Define DMA2_CLEAR_FF_REG 0xD8/* clear pointer flip-flop (w )*/
# Define DMA2_TEMP_REG 0xDA/* Temporary Register (r )*/
# Define DMA2_RESET_REG 0xDA/* Master Clear (w )*/
# Define DMA2_CLR_MASK_REG 0xDC/* Clear Mask */
# Define DMA2_MASK_ALL_REG 0xDE/* all-channels mask (w )*/
The port Address of the Address Register of the eight DMA channels is defined as follows:
# Define DMA_ADDR_0 0x00/* DMA address registers */
# Define DMA_ADDR_1 0x02
# Define DMA_ADDR_2 0x04
# Define DMA_ADDR_3 0x06
# Define DMA_ADDR_4 0xC0
# Define DMA_ADDR_5 0xC4
# Define DMA_ADDR_6 0xC8
# Define DMA_ADDR_7 0xCC
The port address of Count Register for eight DMA channels is defined as follows:
# Define DMA_CNT_0 0x01/* DMA count registers */
# Define DMA_CNT_1 0x03
# Define DMA_CNT_2 0x05
# Define DMA_CNT_3 0x07
# Define DMA_CNT_4 0xC2
# Define DMA_CNT_5 0xC6
# Define DMA_CNT_6 0xCA
# Define DMA_CNT_7 0xCE
The port address of Page Register for eight DMA channels is defined as follows:
# Define DMA_PAGE_0 0x87/* DMA page registers */
# Define DMA_PAGE_1 0x83
# Define DMA_PAGE_2 0x81
# Define DMA_PAGE_3 0x82
# Define DMA_PAGE_5 0x8B
# Define DMA_PAGE_6 0x89
# Define DMA_PAGE_7 0x8A
Several common values of Mode Register are defined as follows:
# Define DMA_MODE_READ 0x44
/* I/O to memory, no autoinit, increment, single mode */
# Define DMA_MODE_WRITE 0x48
/* Memory to I/O, no autoinit, increment, single mode */
# Define DMA_MODE_CASCADE 0xC0
/* Pass thru DREQ-> HRQ, DACK <-HLDA only */
# Define DMA_AUTOINIT 0x10
3.2 read and write DMAC high-level interface functions
(1) enable/disable a specific DMA Channel
The value of bit [2] In the Single Channel Mask Register is 0, which indicates enabling a DMA Channel. The value of 1 indicates disabling a DMA Channel; the bit [1:0] in this register is used to indicate which DMA channel can be enabled or disabled.
The enable_dma () function enables a specific DMA channel to transmit the DMA channel number specified by dmanr. The value range is 0 ~ DMA_MAX_CHANNELS-1. As follows:
Static _ inline _ void enable_dma (unsigned int dmanr)
{
If (dmanr <= 3)
Dma_outb (dmanr, dmaw.mask_reg );
Else
Dma_outb (dmanr & 3, DMA2_MASK_REG );
}
Macros dma_outb and dma_inb are actually outb (or outb_p) and inb functions. Note: When the value of dmanr is greater than 3, it corresponds to the DMA channel 0 ~ on the Master DMAC ~ 3. Therefore, before writing DMA2_MASK_REG, perform operations on dmanr and value 3 to obtain the local channel number on the master DMAC.
The disable_dma () function disables a specific DMA channel. The source code is as follows:
