Implementation of three synchronous FIFO (Verilog implementation) __VERILOG/SV implementation of specific functions

1.Verilog Collation of the FIFO paper notes 2.FIFO, Verilog

Using Verilog to realize two synchronous FIFO methods, it is very suitable for beginners to understand the process and method of timing control.
Understand this thing, a lot of Verilog realize method and thought you will have a deep understanding.
Accumulate slowly.
16*16 fifo//
Method 1

Module FIFO (clock,reset,read,write,fifo_in,fifo_out,fifo_empty,fifo_half,fifo_full);
  Input clock,reset,read,write;
  input [15:0]fifo_in;
  Output[15:0]fifo_out;
  Output fifo_empty,fifo_half,fifo_full;//Mark bit reg [15:0]fifo_out;
  reg [15:0]ram[15:0];

  reg [3:0]read_ptr,write_ptr,counter;//pointer with Count wire fifo_empty,fifo_half,fifo_full;
      always@ (Posedge clock) if (reset) begin read_ptr=0;
      write_ptr=0;
      counter=0;                    fifo_out=0;        Initial value End Else case ({read,write}) 2 ' B00:counter=counter;
              No read/write instruction 2 ' B01://write instruction, data input FIFO begin ram[write_ptr]=fifo_in;
              counter=counter+1;
            Write_ptr= (write_ptr==15) 0:write_ptr+1;
              End 2 ' B10://read instruction, data readout FIFO begin FIFO_OUT=RAM[READ_PTR];
              Counter=counter-1;
          Read_ptr= (read_ptr==15) 0:read_ptr+1;  End 2 ' B11://read/write instruction at the same time, the data can output the begin if (counter==0) directly
              fifo_out=fifo_in;
                  else begin ram[write_ptr]=fifo_in;
                  FIFO_OUT=RAM[READ_PTR];
                  Write_ptr= (write_ptr==15) 0:write_ptr+1;
                Read_ptr= (read_ptr==15) 0:write_ptr+1;    End End Endcase Assign fifo_empty= (counter==0);
        Assign fifo_half= (counter==8) of the symbolic position assignment combined circuit;

    Assign Fifo_full= (counter==15); Endmodule

//4*16 FIFO
//Method 2

Module Fifo_four (CLK,RSTP,DIN,READP,WRITEP,DOUT,EMPTYP,FULLP);                Input CLK;               Clock input RSTP;           Reset Input[15:0]din;              16-bit input signal inputs READP;              Read instruction input writep;         Write instruction Output[15:0]dout;            16-bit output signal emptyp;             NULL indication signal output FULLP;

  Full indicating signal parameter depth=2,max_count=2 ' B11;
  Reg[15:0]dout;
  Reg Emptyp;

  Reg FULLP; reg[(DEPTH-1): 0] tail; Read Pointer reg[(DEPTH-1): 0] head;//write pointer reg[(DEPTH-1): 0] count; Counter Reg[15:0]fifomem[0:max_count];  
    Four 16-bit storage units//read always@ (Posedge clk) if (rstp==1) dout<=0;
   else if (readp==1&&emptyp==0) dout<=fifomem[tail];

  Write always@ (Posedge clk) if (rstp==1&&writep==1&&fullp==0) fifomem[head]<=din;
  Update head pointer always@ (Posedge CLK) if (rstp==1) head<=0;

  else if (writep==1&&fullp==0) head<=head+1; Update tail pointer always@ (posedgeCLK) if (rstp==1) tail<=0;

  else if (readp==1&&emptyp==0) tail<=tail+1;
  Count always@ (Posedge clk) if (rstp==1) count<=0;
     else case ({readp,writep}) 2 ' b00:count<=count;
     2 ' B01:if (count!=max_count) count<=count+1;
     2 ' B10:if (count!=0) count<=count-1;
    2 ' b11:count<=count;
   Endcase//Update flag bit Emptyp always@ (count) if (count==0) emptyp<=1;

  else emptyp<=0;
  Update flag bit tail always@ (count) if (Count==max_count) tail<=1;

else tail<=0; Endmodule

The online code read data output (dataout) section is not read-enabled (RD) control, obviously not, so slightly modified, welcome criticism

Another style of synchronous FIFO

Module Fifo_buffer (data_out, Stack_full, Stack_almost_full, Stack_half_full, Stack_almost_empty, Stack_empty,
  Data_in, Write_to_stack, Read_from_stack, Clk,rst);
  Parameter stack_width=32;
  Parameter stack_height=8;
  Parameter stack_ptr_width=3;
  Parameter ae_level=2;
  Parameter af_level=6;
  Parameter hf_level=4;

  Output [stack_width-1:0] data_out;
  Output stack_full,stack_almost_full,stack_half_full;
  Output stack_almost_empty,stack_empty;
  INPUT[STACK_WIDTH-1:0] data_in;
  Input write_to_stack,read_from_stack;

  Input Clk,rst;

  REG[STACK_PTR_WIDTH-1:0] read_ptr,write_ptr;
  REG[STACK_PTR_WIDTH:0] Ptr_gap;
  REG[STACK_WIDTH-1:0] Data_out;

  REG[STACK_WIDTH-1:0] stack[stack_height-1:0];
  Assign Stack_full= (ptr_gap==stack_height);
  Assign Stack_almost_full= (ptr_gap==af_level);
  Assign Stack_half_full= (ptr_gap==hf_level);
 Assign stack_almost_empty= (ptr_gap==ae_level); Assign stack_empty= (ptr_gap==0);
       Always @ (Posedge CLK or Posedge rst) if (RST) BEGIN data_out<=0;
       read_ptr<=0;
       write_ptr<=0;
   ptr_gap<=0; End else if (Write_to_stack && (!stack_full) && (!read_from_stack)) Begin Stack[write_ptr]<=data_i
       N
       write_ptr<=write_ptr+1;
   ptr_gap<=ptr_gap+1; End Else if ((!write_to_stack) && (!stack_empty) &&read_from_stack) begin Data_out<=stack[read_ptr
       ];
       read_ptr<=read_ptr+1;
   ptr_gap<=ptr_gap-1;
       End else if (Write_to_stack &&read_from_stack&&stack_empty) begin stack[write_ptr]<=data_in;
       write_ptr<=write_ptr+1;
   ptr_gap<=ptr_gap+1;
       End else if (Write_to_stack &&read_from_stack&&stack_full) begin data_out<=stack[read_ptr];
       read_ptr<=read_ptr+1;
   ptr_gap<=ptr_gap-1; End Else if (write_to_stack&&read_from_stack&& (!stack_full) && (!stack_empty)) Begin data_out<=stack[read_ptr];
       stack[write_ptr]<=data_in;
       read_ptr<=read_ptr+1;
   write_ptr<=write_ptr+1;
 End Endmodule