Improve Nc-verilog simulation efficiency with profiler tools

When you do chip verification, you will generally encounter the problem of slow simulation speed and low efficiency.
A method is now found to debug the above problem. That is, using the NC Profiler tool.

With regard to the profiler tool, I post the original document "Cadence®nc-verilog®simulator Help":
The Pro?ler is a tool which measures where CPU time is spent during simulation. Although it is developed primarily to help Cadence R diagnose performance bottlenecks in the simulator, some of the Information in the output, le can help, identify inef?cient HDL coding practices. Once you had determined what code the simulator was spending most of it time running, improving the ef?ciency of this cod E'll has the greatest effect on simulation performance.
The Pro?ler works by interrupting the simulation at regular intervals (currently times per second) and noting Executing at that time. It keeps track of the number of "hits" on different activities, which approximates the amount of CPUs time spent in these a Ctivities.
The Pro?ler are easy to run and have minimal impact on simulation performance and memory usage. To run the Pro?ler, use the-profile command-line option when you invoke the simulator (Ncsim). Use +ncprofile if is running in Single-step invocation mode with the Ncverilog command.

That is, Nc-verilog integrates a profiler tool within the simulation engine that interrupts the emulator 100 times per second and logs it at the end, generating a log file (Ncprof.out) at the conclusion of the simulation.
The most frequently interrupted modules, lines of code, and struct types are listed in the log file, which can help diagnose which code or module is consuming the most time in the simulation.
By modifying these modules, you can improve simulation efficiency. The profiler itself, however, has only a very small effect on simulation.

We open the above function with the-profile option, the simulation command is as follows:

Or

Ncsim–profile Snapshot_name <other_options>

Improve Nc-verilog simulation efficiency with profiler tools