Initial knowledge quartusii 9.0 (cracked, half-additive simulation, synthesis: Next)

Complete the random configuration of the waveform (a, b any given high and low level, just as a test signal), select the taskbar assignments "Setings", set simulation mode for functional, the rest remains unchanged click OK. Click to compile, click to perform the function simulation, the waveform as shown below.

Select the waveform, see the Task column RTL, click to generate a circuit structure based on the waveform, by looking at the circuit, verify that the Verilog program meets the requirements, if not satisfied, in open. v file Modify save then perform a series of simulations without having to re-establish the project. If satisfied, select taskbar assignments "Setings", set simulation mode to timing.

Click the Compile button for comprehensive optimization. The compilation results are as follows:

Select taskbar processing "Generate functional Simulation netlist" to adapt to complete layout and cabling, by netlist Writer generated standard net table file (. vo) and standard delay (. sdo) files, Used for timing simulation of the design (after simulation), after the simulate waveform, you can see the input and output signal there is a delay.

After building the project and design, you can use the Settings dialog box in the Quartus II software Assignment menu,
The assignment Editor, pin Planner, Design partitions window, and Timing Closure layout map Specify initial design constraints, such as PIN assignment, device options, logic options, and timing constraints. Constraints will be on the comprehensive
And the adaptation process produces control and influence. Click Pin Planner to assign pins according to manual

Download debugging: After the design is validated, the target device can be programmed and configured, download the design files to the hardware for hardware verification. The most common programming mode for the Quartusⅱ programmer Programmer is JTAG mode and active serial programming mode as. JTAG mode is mainly used in the debugging phase, the active serial programming mode is used for board level debugging and the user program is cured in the serial configuration chip EPCS. Jpag mode Download: Select the Programmer command under the Tools menu in the Quartusⅱ main window, click Hardware Setup in the dialog box, go to the Hardware Setup dialog, add the hardware device, and after the configuration is complete, Select download mode for JPAG mode. Click on the Start icon to verify.

After the as mode to download, the steps are roughly the same, only need to change mode to Active Serial program, after the download is completed in EPCS, after the Development Board power EPCS will automatically complete the configuration of the target chip, no need to download the program from the computer.

Tips:as mode (active serial configuration mode): Each time the FPGA device is power-up, it acts as a controller to read the data signal from the configuration device EPCs, thereby reading the EPCs data into the FPGA, and realizing the FPGA programming.

JTAG is directly burned into the FPGA because of the SRAM power to re-burn, as is burned into the FPGA configuration chip saved every time the power is written to the FPGA

When downloading the configuration for CYCLONEII devices, such as EP2C8, in the JTAG download mode corresponds. Sof,as download method corresponds to. pof.

Insertion Line Order

1. Power off the FPGA Development Board;

2. Connect the JTAG cable of the JTAG emulator to the JTAG interface of the FPGA Development Board;

3. Plug in the USB cable on the emulator's USB port (assuming another section of the USB cable is plugged into the computer);

4. Turn on the power supply for the FPGA Development Board.

Steps 2 and 3 are best not reversed, because while the FPGA board does not have power, the USB-powered JTAG emulator also generates a certain voltage to be used on the VCC and GND of the FPGA Development Board, so be sure to note this order.

Pull Line Order

1. Power off the FPGA Development Board;

2. Unplug the USB cable from the USB interface of the JTAG emulator;

3. Remove the connection between the JTAG cable and the FPGA Development Board;

Initial knowledge quartusii 9.0 (cracked, half-additive simulation, synthesis: Next)